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STSPIN32G0601 データシート(PDF) 14 Page - STMicroelectronics |
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STSPIN32G0601 データシート(HTML) 14 Page - STMicroelectronics |
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14 / 30 page  Figure 5. Deadtime and interlocking waveforms definition LIN HIN LVG HVG LIN HIN LVG HVG LIN HIN LVG HVG LIN HIN LVG HVG DTLH DTHL DTLH DTHL DTLH DTHL DTLH DTHL gate driver outputs OFF (HALF-BRIDGE TRI-STATE) CONTROL SIGNAL EDGES OVERLAPPED: INTERLOCKING + DEAD TIME CONTROL SIGNALS EDGES SYNCHRONOUS (*): DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, BUT INSIDE THE DEAD TIME: DEAD TIME CONTROL SIGNALS EDGES NOT OVERLAPPED, OUTSIDE THE DEAD TIME: DIRECT DRIVING gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) gate driver outputs OFF (HALF-BRIDGE TRI-STATE) LIN HIN LVG HVG DTLH DTHL gate driver outputs OFF (HALF-BRIDGE TRI-STATE) CONTROL SIGNAL EDGES OVERLAPPED FOR MORE THAN DEAD TIME: INTERLOCKING gate driver outputs OFF (HALF-BRIDGE TRI-STATE) INTERLOCKING INTERLOCKING STSPIN32G0601 Electrical characteristics DS14489 - Rev 1 page 14/30 |
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