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LP1072 データシート(PDF) 13 Page - Freescale Semiconductor, Inc |
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LP1072 データシート(HTML) 13 Page - Freescale Semiconductor, Inc |
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13 / 32 page  LP1072 Interfaces LP1072 Advance Information, Rev. 0.3 Freescale Semiconductor 13 PRELIMINARY Device to SDIO Host Interrupt Enable 0 (0x0017) 7:0 Arm_to_sdio_inte_en[7:0] Individual bit enables for each of the device to host interrupt source bits. Setting the corresponding bit to a “1” enables the interrupt; “0” disables the interrupt. The SDIO Host can disable all interrupts by disabling the main SDIO host interrupt in the CCCR register. - ⎯ RW 0’s Device to SDIO Host Interrupt Enable 1 (0x0018) 2:0 Arm_to_sdio_inte_en[10:8] Individual bit enables for each of the device to host interrupt source bits. Setting the corresponding bit to a “1” enables the interrupt; “0” disables the interrupt. The SDIO Host can disable all interrupts by disabling the main SDIO host interrupt in the CCCR register. Bit 0 is enable for semaphore 0 granted; bit 1 is semaphore 1; and bit 2 is semaphore 2. - ⎯ RW 0’s 7:3 - ⎯ Reserved - ⎯ - ⎯ - ⎯ SDIO Host Mailbox Semaphore 0 Register (offset 0x001C) 1:0 Sdio_mbxp_0_sema 2 bit semaphore register to control whether the host or the device has access to the shared mailbox ram 0. The host should write a “01” to this register to request the shared ram 0. After writing “01” the host should read this register. If the value is “01” then the host owns access to the mailbox. If the value read is “11” then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing “00” to this register. RW RW 0’s 7:2 Reserved - ⎯ - ⎯ - ⎯ - ⎯ SDIO Host Mailbox Semaphore 1 Register (offset 0x001D) 1:0 Sdio_mbxp_1_sema 2 bit semaphore register to control whether the host or the device has access to the shared mailbox ram 1. The host should write a “01” to this register to request the shared ram 1. After writing “01” the host should read this register. If the value is “01” then the host owns access to the mailbox. If the value read is “11” then the device owns access to the mailbox. When the host is done utilizing the mailbox then it should release ownership of the mailbox by writing “00” to this register. RW RW 0’s 7:2 Reserved - ⎯ - ⎯ - ⎯ - ⎯ Table 8. SDIO Function 1 Registers (continued) Bit Name Description ARM Access HOST Access Reset |
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