STK15C68

March 2006

4

Document Control # ML0009 rev 0.2

SRAM WRITE CYCLES #1 & #2

Note i:

If W is low when E goes low, the outputs remain in the high-impedance state.

Note j:

E or W must be

SRAM WRITE CYCLE #1: W Controlledj

SRAM WRITE CYCLE #2: E Controlledj

NO.

SYMBOLS

PARAMETER

STK15C68-25

STK15C68-35

STK15C68-45

UNITS

#1

#2

Alt.

MIN

MAX

MIN

MAX

MIN

MAX

12

Write Cycle Time

25

35

45

ns

13

Write Pulse Width

20

25

30

ns

14

Chip Enable to End of Write

20

25

30

ns

15

Data Set-up to End of Write

10

12

15

ns

16

Data Hold after End of Write

0

0

0

ns

17

Address Set-up to End of Write

20

25

30

ns

18

Address Set-up to Start of Write

0

0

0

ns

19

Address Hold after End of Write

0

0

0

ns

20

h, i

Write Enable to Output Disable

10

13

15

ns

21

Output Active after End of Write

5

5

5

ns

PREVIOUS DATA

DATA OUT

E

ADDRESS

12

W

16

DATA IN

19

13

18

17

DATA VALID

20

15

HIGH IMPEDANCE

21

14

W

DATA OUT

E

ADDRESS

12

W

DATA IN

13

1 7

DATA VALID

HIGH IMPEDANCE

14

18

19

15

16