1999 Jan 06

11

Philips Semiconductors

Product specification

10-bit high-speed low-power ADC

TDA8763A

3. In order to ensure the optimum linearity performance of such converter architecture the lower and upper extremities

of the converter reference resistor ladder (corresponding to output codes 0 and 1023 respectively) are connected to

a) The current flowing into the resistor ladder is

and the full-scale input range at the converter,

to cover code 0 to code 1023, is

will be kept reasonably constant from device to device. Consequently variation of the output

supply voltage. When several ADCs are connected in parallel and fed with the same reference source, the

matching between each of them is then optimized.

4.

5. The analog bandwidth is defined as the maximum input sine wave frequency which can be applied to the device.

No glitches greater than 2 LSBs, neither any significant attenuation are observed in the reconstructed signal.

6. The analog input settling time is the minimum time required for the input signal to be stabilized after a sharp full-scale

input (square wave signal) in order to sample the signal and obtain correct output data.

7. Effective bits are obtained via a Fast Fourier Transform (FFT) treatment taking 8K acquisition points per equivalent

fundamental period. The calculation takes into account all harmonics and noise up to half of the clock frequency

(NYQUIST frequency). Conversion to signal-to-noise ratio: SINAD = ENOB

× 6.02 + 1.76 dB.

8. Intermodulation measured relative to either tone with analog input frequencies of 4.43 MHz and 4.53 MHz. The two

input signals have the same amplitude and the total amplitude of both signals provides full-scale to the converter.

9. Measurement carried out using video analyser VM700A, where the video analog signal is reconstructed through a

digital-to-analog converter.

recommended to have the lowest possible output load.

I

L

V

RT

V

RB

–

R

OB

R

L

R

OT

++

------------------------------------------

=

V

I

R

L

I

L

×

R

L

R

OB

R

L

R

OT

++

------------------------------------------

==

V

(

RT

×

V

RB

–

)

+

0.

˙ 852

V

(

RT

V

–

×

=

RL

ROB

RL

ROT

++

------------------------------------------------

E

G

V

1023

V

0

–

() V

ip

p

–

()

–

V

ip

p

–

()

------------------------------------------------------------

100

×

=

Fig.3 Explanation of note 3.

handbook, halfpage

RLAD

ROT

VRT

VRM

VRB

ROB

code 1023

code 0

MGD281

IL

RL