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TDF8541TH/N2 データシート(PDF) 34 Page - NXP Semiconductors

部品番号 TDF8541TH/N2
部品情報  I 2C-bus controlled 4 x 45 W power amplifier
PDF  54 Pages
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メーカー  NXP [NXP Semiconductors]
ホームページ  http://www.nxp.com
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TDF8541TH/N2 データシート(HTML) 34 Page - NXP Semiconductors

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TDF8541
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 3 — 13 December 2011
34 of 54
NXP Semiconductors
TDF8541
I2C-bus controlled 4
 45 W power amplifier
Start-up/shut-down/mute timing
twake
wake-up time
time after wake-up via pin STB
before first I2C-bus transmission
is recognized; see Figure 4
-
300
500
s
ILO(SVR)
output leakage current on
pin SVR
--
5
A
td(mute_off)
mute off delay time
time from amplifier start to 10 %
of output signal; ILO = 0 A
[2]
I2C-bus mode;
with ILO =5 A  +15 ms;
no DC-load (IB1[D1] = 0); see
Figure 4
-
430
650
ms
legacy mode;
with ILO =5 A  +20 ms;
VSTB =7V; RADSEL =0 ;
see Figure 5
-
430
650
ms
tamp_on
amplifier on time
time from amplifier start to
amplifier on; 90 % of output
signal; ILO = 0 A
[2]
I2C-bus mode;
with ILO =5 A  +30 ms;
no DC-load (IB1[D1] = 0); see
Figure 4
-
550
800
ms
legacy mode;
with ILO =5 A  +20 ms;
VSTB =7V; RADSEL =0 ;
see Figure 5
-
550
800
ms
toff
amplifier switch-off time
time to DC output voltage < 0.1 V;
ILO =0 A
[2]
I2C-bus mode; with
ILO =5 A  +0 ms;
see Figure 4
250
500
750
ms
via pin STB; (IB4[D6] = 0);
with ILO =5 A  +0 ms;
see Figure 5
250
500
750
ms
td(mute-on)
delay time from mute to on
from 10 % to 90 % of output
signal; Vi =50 mV; I2C-bus mode
(IB2[D1] = 1 to 0) or legacy mode
(VSTB = 3 V to 7 V); see Figure 5
5
1540ms
td(soft_mute)
soft mute delay time
from 90 % to 10 % of output
signal; Vi =50 mV; I2C-bus mode
(IB2[D1] = 0 to 1) or legacy mode
(VSTB = 7 V to 3 V); see Figure 5
5
1540ms
td(fast_mute)
fast mute delay time
from 90 % to 10 % of output
signal; Vi =50 mV; I2C-bus mode
(IB2[D0] = 0 to 1, or VSTB from
> 5.9 V to < 0.8 V in 1
s; see
Figure 5
-0.4
1
ms
Table 20.
Characteristics …continued
Refer to test circuit (see Figure 29) at Tamb =25 C; VP = 14.4 V; unless otherwise specified. Tested at Tamb =25 C;
guaranteed for Tj = 40 C to +150 C; functionality is guaranteed for VP < 10 V unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit



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