TUSB564 datasheet(24/52 Pages) TI

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7.4.6 Operation Timing – Power Up

d_pg

VCC

Internal

Power

Good

T Cfg_su

TCfg_hd

DISABLED

USB3.1- only

FLIP = 0

If (( CTL[1:0 ] ==2'b 00 | CTL[1:0 ] ==2'b 01 ) & FLIP == 0 ) {

USB3.1- only no FLIP;

} ELSEIF((CTL[1:0 ] ==2'b 00 | CTL[1:0 ] ==2'b01 ) & FLIP == 1 ){

USB3.1- only with FLIP ;

} ELSEIF(CTL[1:0 ] ==2'b 10 & FLIP ==0 ) {

4-Lane DP no FLIP;

} ELSEIF(CTL[1:0 ] ==2'b 10 & FLIP ==1 ){

4-Lane DP with FLIP ;

} ELSEIF(CTL[1:0 ] ==2'b 11 & FLIP ==0 ) {

2-Lane DP USB3.1 no FLIP;

} ELSE{

2-Lane DP USB3.1 with FLIP ;

};

CTL[1:0 ] pins

FLIP pin

CFG pins

In GPIO mode

DISABLED

USB3.1- only

FLIP = 0

In I2C mode

Mode of operation

determined by value of

FLIPSEL bit and CTLSEL[1:0]

bits at offset0x0A. Default

is USB3.1- only no Flip.

Tctl_db

CC (min)

Figure 7-1. Power-Up Timing

Table 7-8. Power-Up Timing (1) (2)

PARAMETER

MIN

MAX

UNIT

td_pg

VCC (minimum) to Internal Power Good asserted high

500

µs

tcfg_su

CFG(1) pins setup(2)

µs

tcfg_hd

CFG(1) pins hold

µs

tCTL_DB

CTL[1:0] and FLIP pin debounce

tVCC_RAMP

VCC supply ramp requirement

0.1

(1)

Following pins comprise CFG pins: I2C_EN, EQ[1:0], SSEQ[1:0], and DPEQ[1:0].

(2)

Recommend CFG pins are stable when VCC is at minimum value.

TUSB564-Q1

SLLSFO9A – MAY 2024 – REVISED SEPTEMBER 2024

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