TLE2072, TLE2072A, TLE2072Y

EXCALIBUR LOW-NOISE HIGH-SPEED

JFET-INPUT DUAL OPERATIONAL AMPLIFIERS

SLOS124A – JUNE 1993 – REVISED AUGUST 1994

5–3

POST OFFICE BOX 655303

TLE2072Y chip information

This chip, when properly assembled, displays characteristics similar to the TLE2072. Thermal compression or

ultrasonic bonding may be used on the doped-aluminum bonding pads. Chips may be mounted with conductive

epoxy or a gold-silicon preform.

BONDING PAD ASSIGNMENTS

CHIP THICKNESS: 15 TYPICAL

BONDING PADS: 4

× 4 MINIMUM

TJmax = 150°C

TOLERANCES ARE

±10%.

ALL DIMENSIONS ARE IN MILS.

PIN (4) IS INTERNALLY CONNECTED

TO BACKSIDE OF THE CHIP.

+

–

1OUT

1IN +

1IN –

VCC+

(4)

(6)

(3)

(2)

(5)

(1)

(7)

(8)

–

+

2OUT

2IN +

2IN –

VCC –

80

90

(1)

(2)

(3)

(4)

(5)

(6)

(7)

(8)