AD8311 datasheet(20/24 Pages) AD

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AD8311

Rev. A | Page 20 of 24

EVALUATION BOARD

Figure 41 shows the schematic of the AD8311 WLCSP

evaluation board. The layout and silkscreen of the component

and circuit sides are shown in Figure 42 to Figure 45. The board

is powered by a single supply in the range 2.7 V to 5.5 V. The

power supply is decoupled by a 0.1 μF capacitor. A 100 pF

capacitor provides additional supply decoupling, but is not

necessary for basic operation.

Table 5 details the various configuration options of the

evaluation board.

For operation in controller mode, both jumpers J1 and J2

should be removed. The setpoint voltage is applied to VSET,

RFIN is connected to the RF source (PA output or directional

coupler), and VAPC is connected to the gain control pin of the

PA. When used in controller mode, a capacitor must be

installed in C4 for loop stability (R2 must also be installed, 0 Ω

by default). For GSM/DCS handset power amplifiers, this

capacitor should typically range from 150 pF to 300 pF.

A quasi-measurement mode (where the AD8311 delivers an

output voltage that is proportional to the log of the input signal)

can be implemented, to establish the relationship between VSET

and RFIN, by installing the two jumpers J1 and J2. This mimics

an AGC loop. To establish the transfer function of the log amp,

the RF input should be swept while the voltage on VSET is

measured, that is, the SMA connector labeled VSET now acts as

an output. This is the simplest method to validate operation of

the evaluation board. When operated in this mode, a large

capacitor (0.01 μF or greater) must be installed in C4 (filter

capacitor) to ensure loop stability. The op amp must be powered

with a nominal voltage of 2.7 V to 5.5 V with the VS supply.

Alternately, J3 can be installed to power the op amp with the

AD8311’s VPOS power supply.

VAPC

VPOS

AD8311

VSET

COMM

RFIN

FTLR

100pF

0.1

μF

52.3

VPOS

RFIN

VAPC

(OPEN)

R10

(OPEN)

10k

17.8k

(OPEN)

TO EDGE

CONNECTOR

10k

16.2k

VPOS

0.1

μF

0.1

μF

VSET

(OPEN)

TO EDGE

CONNECTOR

Figure 41. Evaluation Board Schematic

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