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P89V52X2FN データシート(PDF) 13 Page - NXP Semiconductors |
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P89V52X2FN データシート(HTML) 13 Page - NXP Semiconductors |
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13 / 56 page ![]() P89V52X2_1 © NXP B.V. 2007. All rights reserved. Preliminary data sheet Rev. 01 — 7 June 2007 13 of 56 NXP Semiconductors P89V52X2 80C51 with 256 B RAM, 192 B data EEPROM 6.5 Dual data pointers The device has two 16-bit data pointers. The DPTR Select (DPS) bit in AUXR1 determines which of the two data pointers is accessed. When DPS = 0, DPTR0 is selected; when DPS = 1, DPTR1 is selected. Quickly switching between the two data pointers can be accomplished by a single INC instruction on AUXR1 (see Figure 8). Table 7. AUXR - Auxiliary register (address 8EH) bit description Bit Symbol Description 7 to 1 - Reserved for future use. Should be set to ‘0’ by user programs. 0 AO ALE off: disables/enables ALE. AO = 0 results in ALE emitted at a constant rate of 1 ⁄ 2 the oscillator frequency. In case of AO = 1, ALE is active only during a MOVX or MOVC. Fig 7. Internal and external data memory structure 00H FFH UPPER 128 B INTERNAL RAM LOWER 128 B INTERNAL RAM (INDIRECT AND DIRECT ADDRESSING) (INDIRECT ADDRESSING) (DIRECT ADDRESSING) SPECIAL FUNCTION REGISTERS (SFRs) 80H FFH FFFFH EXTERNAL DATA MEMORY 0000H (INDIRECT ADDRESSING) 80H 7FH 002aac567 Fig 8. Dual data pointer organization Table 8. AUXR1 - Auxiliary register 1 (address A2H) bit allocation Not bit addressable; Reset value 00H Bit 7 6 5 4 3 2 1 0 Symbol -- -- GF2 0 -DPS DPL 82H DPS = 0 → DPTR0 DPS = 1 → DPTR1 external data memory DPS 002aaa518 DPH 83H DPTR0 DPTR1 AUXR1 / bit0 |
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