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STR750FV0 データシート(PDF) 35 Page - STMicroelectronics |
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STR750FV0 データシート(HTML) 35 Page - STMicroelectronics |
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35 / 81 page  STR750Fxx STR751Fxx STR752Fxx STR755Fxx Electrical parameters 35/81 5.3.3 Embedded voltage regulators Subject to general operating conditions for VDD_IO, and TA Table 12. Embedded voltage regulators Symbol Parameter Conditions Min Typ Max Unit VMVREG MVREG power supply(1) 1. VMVREG is observed on the V18, V18REG and V18BKP pins except in the following case: - In STOP mode with MVREG OFF (LP_PARAM13 bit). See note 2. - In STANDBY mode. See note 2. load <150 mA 1.65 1.80 1.95 V VLPVREG LPVREG power supply(2) 2. In STANDBY mode, VLPVREG is observed on the V18BKP pin In STOP mode, VLPVREG is observed on the V18, V18REG and V18BKP pins. load <10 mA 1.30 1.40 1.50 V tVREG_PWRUP (1) Voltage Regulators start-up time (to reach 90% of final V18 value) at VDD_IO power-up (3) 3. Once VDD_IO has reached 3.0 V, the RSM (Regulator Startup Monitor) generates an internal RESET during this start-up time. VDD_IO rise slope = 20 µs/V 80 µs VDD_IO rise slope = 20 ms/V 35 ms |
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