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MCS7840
USB-2.0 to Four Serial Ports
Rev.
1.2
Page 9
UART Register-Set and Register Descriptions
The UART has 10 registers, but only three address lines to access those registers. The mapping of the
registers is dependent upon the Line Control Register (LCR).
LCR[7] enables the Divider Latch Registers (DLL & DLM).
The following table gives the various UART registers and their offsets.
Register
Name
Offset R/W Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
THR
0
W
Data to be transmitted ( Transmitter Holding Register)
RHR
0
R
Data to be received (Receiver Holding Register)
IER
1
R/W
Reserved
Sleep
Mode
Modem
Int
Mask
Rx
Stat
Int
Mask
Tx Rdy
Int
Mask
Rx Rdy
Int
Mask
FCR
2
W
RHR
Trigger Level
Reserved
Reserved
Flush
THR
Flush
RHR
FIFO
Enable
ISR
2
R
FIFOs
Enabled
Reserved
Interrupt Priority
Interrupt
Pending
LCR
3
R/W
DLE
Tx
Break
Force
Parity
Odd/Even
Parity
Parity
Enable
Stop
Bits
Data Length
MCR
4
R/W
DTR – DSR/
DCD
Flow Control
RTS/CTS
Flow
Control
Loop
Unused
RTS
DTR
LSR
5
R
Data
Error
Tx
Empty
THR
Empty
Rx
Break
Framing
Error
Parity
Error
Overrun
Error
Rx
Rdy
MSR
6
R
DCD
RI
DSR
CTS
ΔDCD
Teri
ΔDSR
ΔCTS
SPR
7
R/W
Scratch Pad Register
Additional standard registers - these are accessed when LCR[7] = 1
DLL
0
R/W
Divisor Latch bits[7:0]
DLM
1
R/W
Divisor Latch bits[15:8]
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