HT46R46E datasheet(21/73 Pages) HOLTEK

21 / 73 page

HT46R46E/C46E/R47E/C47E/R48AE/C48AE/R49E

Rev. 1.20

August 15, 2007

Input/Output Ports

Holtek microcontrollers offer considerable flexibility on

their I/O ports. With the input or output designation of ev-

ery pin fully under user program control, pull-high op-

tions for all ports and wake-up options on certain pins,

the user is provided with an I/O structure to meet the

needs of a wide range of application possibilities.

Depending upon which device or package is chosen,

the microcontroller range provides from 13 to 23

bidirectional input/output lines labeled with port names

PA, PB, PC and PD. These I/O ports are mapped to the

RAM Data Memory with specific addresses as shown in

the Special Purpose Data Memory table. All of these I/O

ports can be used for input and output operations. For

input operation, these ports are non-latching, which

means the inputs must be ready at the T2 rising edge of

instruction

²MOV A,[m]², where m denotes the port ad-

dress. For output operation, all the data is latched and

remains unchanged until the output latch is rewritten.

Pull-high Resistors

Many product applications require pull-high resistors for

their switch inputs usually requiring the use of an exter-

nal resistor. To eliminate the need for these external re-

sistors, all I/O pins, when configured as an input have

the capability of being connected to an internal pull-high

resistor. These pull-high resistors are selectable via

configuration options and are implemented using a

weak PMOS transistor.

Port A Wake-up

Each device has a HALT instruction enabling the

microcontroller to enter a Power Down Mode and pre-

serve power, a feature that is important for battery and

other low-power applications. Various methods exist to

wake-up the microcontroller, one of which is to change

the logic condition on one of the Port A pins from high to

low. After a

²HALT² instruction forces the microcontroller

into entering a HALT condition, the processor will re-

main idle or in a low-power state until the logic condition

of the selected wake-up pin on Port A changes from high

to low. This function is especially suitable for applica-

tions that can be woken up via external switches. Note

that each pin on Port A can be selected individually to

have this wake-up feature.

I/O Port Control Registers

Each I/O port has its own control register PAC, PBC,

PCC and PDC, to control the input/output configuration.

With this control register, each CMOS output or input

with or without pull-high resistor structures can be re-

configured dynamically under software control. Each pin

of the I/O ports is directly mapped to a bit in its associ-

ated port control register. For the I/O pin to function as

an input, the corresponding bit of the control register

must be written as a

²1². This will then allow the logic

state of the input pin to be directly read by instructions.

When the corresponding bit of the control register is

written as a

²0², the I/O pin will be setup as a CMOS out-

put. If the pin is currently setup as an output, instructions

can still be used to read the output register. However, it

should be noted that the program will in fact only read

the status of the output data latch and not the actual

logic status of the output pin.

Pin-shared Functions

The flexibility of the microcontroller range is greatly en-

hanced by the use of pins that have more than one func-

tion. Limited numbers of pins can force serious design

constraints on designers but by supplying pins with

multi-functions, many of these difficulties can be over-

come. For some pins, the chosen function of the

multi-function I/O pins is set by configuration options

while for others the function is set by application pro-

gram control.

EEPROM Timing Diagram

The Timing Diagram shows in more detail the timing re-

lationship between SCL and SDA. The specific timing

values are provided in the EEPROM A.C. Characteris-

tics table. These timings must be carefully managed by

the programmer during application program develop-

ment, especially if the device is used at higher clock

speeds.

t f

t L O W

t r

t H I G H

t S U : S T A

t H D : S T A

t S P

t H D : D A T

t S U : D A T

t S U : S T O

t B U F

V a l i d

S C L

S D A

O U T

t A A

Timing Diagram

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