M58PR256J datasheet(53/114 Pages) STMICROELECTRONICS

部品番号	M58PR256J

部品情報	256 Mbit or 512 Mbit (x16, Multiple Bank, Multilevel, Burst) 1.8 V supply Flash memories

PDF	114 Pages

Scroll/Zoom	100%

メーカー	STMICROELECTRONICS [STMicroelectronics]

ホームページ	http://www.st.com

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53 / 114 page

M58PR256J, M58PR512J

Configuration Register

53/114

Figure 6.

X-latency and data output configuration example

The settings shown are X-latency = 4. tQVK_CPU is the data setup time required by the system CPU.

Amax is equal to A23 in the M58PR256J and, to A24 in the M58PR512J.

Table 16.

Burst type definition

Start Address

8 Words

16 Words

Continuous Burst

0-1-2-3-4-5-6-7

0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15

0-1-2-3-4-5-6...

1-2-3-4-5-6-7-0

1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0

1-2-3-4-5-6-7...

2-3-4-5-6-7-0-1

2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1

2-3-4-5-6-7-8...

3-4-5-6-7-0-1-2

3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2

3-4-5-6-7-8-9...

...

7-0-1-2-3-4-5-6

7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6

7-8-9-10-11-12-13...

...

12-13-14-15-8-9-10-11

12-13-14-15-0-1-2-3-4-5-6-7-8-9-10-11

12-13-14-15-16-17...

13-14-15-8-9-10-11-12

13-14-15-0-1-2-3-4-5-6-7-8-9-10-11-12

13-14-15-16-17-18...

14-15-8-9-10-11-12-13

14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13

14-15-16-17-18-19...

15-8-9-10-11-12-13-14

15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14

15-16-17-18-19-20...

AI08904c

Amax-A0(1)

VALID ADDRESS

DQ15-DQ0

VALID DATA

X-latency

VALID DATA

1st cycle

2nd cycle

3rd cycle

4th cycle

tKHKH

tQVK_CPU

tKHQV

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