ADS8317IBDRBT datasheet(22/29 Pages) TI

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POWER DISSIPATION

Short Cycling

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

There

important

distinction

between

the

power-down mode that is entered after a conversion

The architecture of the converter, the semiconductor

is complete and the full power-down mode that is

fabrication process, and a careful design allow the

enabled when CS is high. CS low only shuts down

ADS8317 to convert at up to a 250kHz rate while

the analog section. The digital section completely

requiring very little power. However, for the absolute

shuts down only when CS is high. Thus, if CS is left

lowest power dissipation, there are several things to

low at the end of a conversion, and the converter is

keep in mind.

continually clocked, the power consumption is not as

low as when CS is high.

The power dissipation of the ADS8317 scales directly

with conversion rate. Therefore, the first step to

achieving the lowest power dissipation is to find the

lowest conversion rate that satisfies the system

Another way to save power is to use the CS signal to

requirements.

short-cycle the conversion. The ADS8317 places the

latest data bit on the DOUT line as it is generated;

In addition, the ADS8317 goes into Power-Down

therefore, the converter can easily be short-cycled.

mode under two conditions: when the conversion is

This term means

that

the

conversion

can

complete and whenever CS is high (see the Timing

terminated at any time. For example, if only 14 bits of

Characteristics section). Ideally, each conversion

the conversion result are needed, then the conversion

should occur as quickly as possible, preferably at a

can be terminated (by pulling CS high) after the 14th

6.0MHz clock rate. This way, the converter spends

bit has been clocked out.

the longest possible time in power-down mode. This

is very important because the converter not only uses

This technique can also be used to lower the power

power on each DCLOCK transition (as is typical for

dissipation (or to increase the conversion rate) in

digital CMOS components), but also uses some

those applications where an analog signal is being

current

for

the

analog

circuitry,

such

the

monitored until some condition becomes true. For

comparator. The analog section dissipates power

example, if the signal is outside a predetermined

continuously until power-down mode is entered.

range, the full 16-bit conversion result may not be

needed. If so, the conversion can be terminated after

Figure

and

Figure

illustrate

the

current

the first n bits, where n might be as low as 3 or 4.

consumption of the ADS8317 versus sample rate. For

This technique results in lower power dissipation in

these graphs, the converter is clocked at maximum

both the converter and the rest of the system

speed regardless of the sample rate. CS is held high

because they spend more time in power-down mode.

during the remaining sample period.

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