ADS8317IB3 datasheet(16/29 Pages) TI

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THEORY OF OPERATION

ANALOG INPUT

ADS8317

Single-EndedInput

Common

Voltage

REF

Peak-to-Peak

DifferentialInput

Common

Voltage

REF

Peak-to-Peak

REF

Peak-to-Peak

ADS8317

SBAS356A – JUNE 2007 – REVISED SEPTEMBER 2007

The digital data that are provided on the DOUT pin are

The ADS8317 is a classic Successive Approximation

for the conversion currently in progress—there is no

pipeline delay. It is possible to continue to clock the

architecture is based on capacitive redistribution that

ADS8317 after the conversion is complete and to

inherently includes a sample-and-hold function. The

obtain the serial data least significant bit first. See the

converter is fabricated on a 0.6

μ CMOS process. The

Digital Timing section for more information.

architecture

and

fabrication

process

allow

the

ADS8317 to acquire and convert an analog signal at

250,000

conversions

per

second

while

consuming less than 10mW from VDD.

The analog input is bipolar and fully differential. There

are two general methods of driving the analog input

Differential

linearity

for

the

ADS8317

of the ADS8317: single-ended or differential, as

factory-adjusted via a package-level trim procedure.

shown in Figure 37. When the input is single-ended,

The state of the trim elements is stored in non-volatile

the –IN input is held at a fixed voltage. The +IN input

memory and is continuously updated after each

swings

around

the

same

voltage

and

the

acquisition cycle, just prior to the start of the

peak-to-peak amplitude is 2

× V

REF. The value of

successive approximation operation. This process

VREF determines the range over which the common

ensures that one complete conversion cycle always

voltage may vary, as shown in Figure 39 and

returns the part to its factory-adjusted state in the

Figure 38.

event of a power interruption.

The ADS8317 requires an external reference, an

external clock, and a single power source (VDD). The

external reference can be any voltage between 0.1V

and VDD/2. The value of the reference voltage directly

sets the range of the analog input. The reference

input current depends on the conversion rate of the

ADS8317.

The external clock can vary between 24kHz (1kHz

throughput) and 6.0MHz (250kHz throughput). The

duty cycle of the clock is not significant, as long as

the minimum high and low times are at least 200ns

(VDD = 4.75V or greater). The minimum clock

frequency is set by the leakage on the internal

capacitors to the ADS8317.

The analog input is provided to two input pins: +IN

and

–IN.

When

conversion

initiated,

the

differential input on these pins is sampled on the

Figure 37. Methods of Driving the

internal capacitor array. While a conversion is in

ADS8317—Single-Ended or Differential

progress, both inputs are disconnected from any

internal function.

The digital result of the conversion is clocked out by

the DCLOCK input and is provided serially (most

significant bit first) on the DOUT pin.

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