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GL9714 データシート(PDF) 39 Page - GENESYS LOGIC

部品番号 GL9714
部品情報  PCI ExpressTM PIPE x4 PHY
PDF  46 Pages
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メーカー  GENESYS [GENESYS LOGIC]
ホームページ  http://www.genesyslogic.com
Logo GENESYS - GENESYS LOGIC

GL9714 データシート(HTML) 39 Page - GENESYS LOGIC

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GL9714 PCI Express
TM PIPE x4 PHY
©2004-2007 Genesys Logic Inc. - All rights reserved.
Page 39
7.5 Differential Transmitter and Receiver Serial Output
Transmitter Serial Output
Table 7.6 – Transmitter Serial Output
Symbol
Parameter
Min
Typ
Max
Unit
UI
Unit interval
399.88
400
400.12
ps
VTX-DIFFp-p
Differential peak to peak output voltage
0.8
-
1.2
V
VTX-DE-RATIO
De-emphasized
differential
output
voltage (Ratio)
-3.0
-3.5
-4.0
dB
TTX-EYE
Minimum TX eye width
0.7
-
-
UI
TTX-EYE-MEDIAN-to-MAX-JITTER
Maximum
time
between
the
jitter
median and maximum deviation from
the median
-
-
0.15
UI
TTX-RISE,
TTX-FALL
D+/D- TX output rise/fall time
0.125
-
-
UI
VTX-CM-ACp
RMS AC peak common mode output
voltage
-
-
20
mV
VTX-CM-DC-ACTIVE-IDLE-DELTA
Absolute delta of DC common mode
voltage during L0 and electrical idle
0
-
100
mV
VTX-CM-DC-LINE-DELTA
Absolute delta of DC common mode
voltage between D+ and D-
0
-
25
mV
VTX-IDLE-DIFFp
Electrical idle differential peak output
voltage
0
-
20
mV
VTX-RCV-DETECT
The amount of voltage change allowed
during receiver detection
-
-
600
mV
VTX-DC-CM
The TX DC common mode voltage
0
-
3.6
V
ITX-SHORT
TX short circuit current limit
-
-
90
mA
TTX-IDLE-MIN
Minimum time spent in electrical idle
50
-
-
UI
TTX-IDLE-SET-TO-IDLE
Maximum time to transition to a valid
electrical idle after sending an electrical
idle ordered set
-
-
20
UI
TTX-IDLE-TO-DIFF-DATA
Maximum time to transition to valid TX
specifications after leaving an electrical
idle condition
-
-
20
UI
RLTX-DIFF
Differential return loss
12
-
-
dB
RLTX-CM
Common mode return loss
6
-
-
dB
ZTX-DIFF-DC
DC differential TX impedance
80
100
120
Ω
LTX-SKEW
Lane-to-lane output skew
-
-
500 + 2UI
ps
CTX
AC coupling capacitor
75
-
200
nF
Tcrosslink
Crosslink random timeout
0
-
1
ms



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