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Issue A

LANSDALE Semiconductor, Inc.

ML12210

DATA ENTRY FORMAT

The three wire interface of DATA pin, CLK (clock) pin and LE (load enable) pin controls the serial data input of the 14–bit programma-

ble reference divider plus the prescaler setting bit, and the 18–bit programmable divider. A rising edge of the clock shifts one bit of serial

data into the internal shift registers. Depending upon the level of the control bit, stored data is transferred into the latch when load enable

pin is HIGH or OPEN.

Control bit:

“H” = data is transferred into 15–bit latch of programmable reference divider

“L” = data is transferred into 18–bit latch of programmable divider

WARNING: Switching CLK or DATA after the device is programmed may generate noise on the charge pump outputs which will affect

the VCO.

PROGRAMMABLE REFERENCE DIVIDER

16–bit serial data format for the programmable reference counter, “R–counter”, and prescaler select bit (SW) is shown below. If the con-

trol bit is HIGH, data is transferred from the 15–bit shift register into the 15–bit latch which specifies the R divide ratio (8 to16383) and

the prescaler divide ratio (SW=0 for ÷64/65, SW=1 for ÷32/33). An R divide ratio less than 8 is prohibited.

For Control bit (C) = HIGH:

C

R

1

R

2

R

3

R

4

R

5

R

6

R

7

R

8

R

9

R

10

R

11

R

12

R

13

R

14

S

W

SETTING BITS FOR DIVIDE RATIO OF PROGRAMMABLE

REFERENCE COUNTER (R–COUNTER)

MSB

SETTING BIT FOR PRESCALER DIVIDE RATIO (FIRST BIT)

LSB

CONTROL BIT (LAST BIT)

DIVIDE RATIO OF PROGRAMMABLE REFERENCE (R) COUNTER

Divide

Ratio R

R

14

R

13

R

12

R

11

R

10

R

9

R

8

R

7

R

6

R

5

R

4

R

3

R

2

R

1

8

0

0

0

0

0

0

0

0

0

0

1

0

0

0

9

0

0

0

0

0

0

0

0

0

0

1

0

0

1

•

•

•

•

•

•

•

•

•

•

•

•

•

•

•

16383

1

1

1

1

1

1

1

1

1

1

1

1

1

1

PRESCALER SELECT BIT

Prescaler Divide Ratio P

SW

64/65

0

32/33

1