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Advanced CMOS TTL Input – 74ACT574

Rev 1.0

19/3/2021

Timing Requirements6

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

Minimum

Setup Time,

D to CLK

(Figure 2,4)

tSU

5V ±0.5

CL = 50pF,

Input tf =tr= 3ns

2.5

2.5

2.5

ns

Minimum

Hold Time,

CLK to D

(Figure 2,4)

th

5V ±0.5

CL = 50pF,

Input tf =tr= 3ns

1.0

1.0

1.0

ns

Minimum

Pulse Width,

CLK

(Figure 2,4)

tw

5V ±0.5

CL = 50pF,

Input tf =tr= 3ns

3.0

4.0

4.0

ns

Switching Waveforms

Figure 4 – Timing Requirements

Figure 3 – Propagation Delay - Output Enable to Q

Figure 1 – Propagation Delay & Output Transition Time