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DF6808 データシート(PDF) 4 Page - Digital Core Design |
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DF6808 データシート(HTML) 4 Page - Digital Core Design |
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4 / 9 page ![]() All trademarks mentioned in this document are trademarks of their respective owners. Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved. http://www.DigitalCoreDesign.com http://www.dcd.pl PINS DESCRIPTI O N PIN ACTIVE TYPE DESCRIPTION clk - input Global system clock rst Low input Global system reset prgdata[7:0] - input Program memory bus input datai[7:0] - input Memory bus input ufrdatai[7:0] - input UFRs data bus input ready Low input Code and Data memory Ready irq * input Interrupt input portai[7:0] - input Port A input portbi[7:0] - input Port B input portci[7:0] - input Port C input portdi[7:0] - input Port D input cap1,2 Low input Capture inputs rxd Low input SCI receiver data input si High input SPI slave input mi High input SPI master input scki * input SPI clock input ss Low input SPI slave select clkdocd - input DoCD TM clock input docddatai - input DoCD TM serial Data input prgaddr[15:0] - output Program memory address bus prgoe - output Program memory output enable datao[7:0] - output Data memory & UFR bus output addr[15:0] - output Data memory address bus ramwe Low output Data memory write enable ramoe Low output Data memory output enable ufraddr[5:0] - output UFR’s address bus ufrwe Low output UFRs write enable ufroe Low output UFRs output enable halt High output Halt clock system (STOP inst.) portao[7:0] - output Port A output portbo[7:0] - output Port B output portco[7:0] - output Port C output portdo[7:0] - output Port D output ddra[7:0] - output Port A data direction control ddrb[7:0] - output Port B data direction control ddrc[7:0] - output Port C data direction control ddrd[7:0] - output Port D data direction control cmp1,2 * output Compare outputs txd Low output SCI transmitter data output so High output SPI slave output mo High output SPI master output scko * output SPI clock output sckz High output Disconnect SPI clock output docddatao - output DoCD TM Serial Data Output docdclk - output DoCD TM Serial Clock Output prgwe - output DoCD TM Program Memory Write * Kind of activity is configurable SYMBOL addr(15:0) ramwe ramoe portao(7:0) portdo(7:0) portco(7:0) portbo(7:0) portai(7:0) portbi(7:0) portci(7:0) portdi(7:0) datai(7:0) ufrdatai(7:0) irq cap1 cap2 clk rst rxd datao(7:0) txd halt ddra(7:0) ddrd(7:0) ddrc(7:0) ddrb(7:0) cmp1 cmp2 prgdata(7:0) prgaddr(15:0) prgoe ready ufraddr(5:0) ufrwe ufroe clkdocd docddatai docddatao docdclk prgwe DoCD TM Interface si mi so mo scki scko sckz ss |
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