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TMP86FS23UG データシート(PDF) 77 Page - Toshiba Semiconductor |
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TMP86FS23UG データシート(HTML) 77 Page - Toshiba Semiconductor |
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77 / 252 page ![]() Page 65 TMP86FS23UG Note: The port placed in input mode reads the pin input state. Therefore, when the input and output modes are used together, the output latch contents for the port in input mode might be changed by executing a bit manipulation instruction. P8DR (0008H) R/W 76 543 21 0 P87 SEG0 P86 SEG1 P85 SEG2 P84 SEG3 P83 SEG4 P82 SEG5 P81 SEG6 P80 SEG7 (Initial value: 0000 0000) P8LCR (0FA1H) 76 543 21 0 (Initial value: 0000 0000) P8LCR P8 port segment output control (Specified for each bit) 0: Input/Output port 1: LCD segment output R/W P8CR (0024H) 76 543 21 0 (Initial value: 0000 0000) P8CR P8 port input/output control (Specified for each bit) 0: Input mode 1: Output mode R/W |
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