TMP86FS28DFG datasheet(130/272 Pages) TOSHIBA

130 / 272 page

Page 118

9. 8-Bit TimerCounter (TC3, TC4)

9.1 Configuration

TMP86FS28DFG

Figure 9-2 8-Bit Timer Mode Timing Chart (TC4)

9.3.2 8-Bit Event Counter Mode (TC3, 4)

In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin.

When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and

the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input

pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin.

Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24

Hz in the SLOW1/2 or SLEEP1/2 mode.

Note 1: In the event counter mode, fix TCjCR<TFFj> to 0. If not fixed, the PDOj, PWMj and PPGj pins may output

pulses.

Note 2: In the event counter mode, do not change the TTREGj setting while the timer is running. Since TTREGj is

not in the shift register configuration in the event counter mode, the new value programmed in TTREGj is in

effect immediately after the programming. Therefore, if TTREGi is changed while the timer is running, an

expected operation may not be obtained.

Note 3: j = 3, 4

Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4)

9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)

This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin.

In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter

and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and

the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the

timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by

TCjCR<TFFj>. Upon reset, the timer F/Fj value is initialized to 0.

To use the programmable divider output, set the output latch of the I/O port to 1.

n-1

n 0

n-1

Internal

Source Clock

Counter

Match detect

Counter clear

Match detect

Counter clear

TC4CR<TC4S>

TTREG4

INTTC4 interrupt request

n-1

n 0

Counter

Match detect

Counter

clear

n-1

Match detect

Counter

clear

TC4CR<TC4S>

TTREG4

INTTC4 interrupt request

TC4 pin input

TMP86FS28DFG データシート(PDF) 130 Page - Toshiba Semiconductor

TMP86FS28DFG データシート(HTML) 130 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシートダウンロード

リンク URL

TMP86FS28DFG データシート(PDF) 130 Page - Toshiba Semiconductor

TMP86FS28DFG データシート(HTML) 130 Page - Toshiba Semiconductor

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

データシート ダウンロード

リンク URL

データシートダウンロード