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TMP86FS28DFG データシート(PDF) 131 Page - Toshiba Semiconductor |
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TMP86FS28DFG データシート(HTML) 131 Page - Toshiba Semiconductor |
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131 / 272 page  Page 119 TMP86FS28DFG Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR<TFFj> after the timer is stopped. Do not change the TCjCR<TFFj> setting upon stopping of the timer. Example: Fixing the PDOj pin to the high level when the TimerCounter is stopped CLR (TCjCR).3: Stops the timer. CLR (TCjCR).7: Sets the PDOj pin to the high level. Note 3: j = 3, 4 Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD (TTREG4), 3DH : 1/1024 ÷27/fc÷2 = 3DH LD (TC4CR), 00010001B : Sets the operating clock to fc/27, and 8-bit PDO mode. LD (TC4CR), 00011001B : Starts TC4. |
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