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STA538B データシート(PDF) 20 Page - STMicroelectronics

部品番号 STA538B
部品情報  2 x 1.3 W class-D amplifier with analog or digital input 2.0 multichannel digital audio processor with FFX
PDF  59 Pages
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メーカー  STMICROELECTRONICS [STMicroelectronics]
ホームページ  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STA538B データシート(HTML) 20 Page - STMicroelectronics

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PLL
STA538
20/59
PLL filter
Figure 5 shows the PLL filter scheme. Recommended values are R1 = 12.5 k
Ω,
C1 = 250 pF, and C2 = 82 pF.
Figure 5.
PLL filter scheme
Table 10 on page 14 gives a typical lock time value for the PLL.
5.2
Configuration examples
The STA538 PLL can be configured in two ways:
●
default startup configuration
●
direct PLL programming
The default startup configuration reads the device’s defaults. With this configuration, it is not
necessary to program the PLL dividers directly as some presets are used. In this mode, the
oversampling ratio between pins XTI (or MCLK33) and LRCLKI is fixed to 256.
The direct PLL programming bypasses the automatic presets allowing direct programming
of the PLL dividers.
The output PLL frequency can be determined as following:
Output division factor:
ODF = 2
Relation between input and output clock frequency:
FINFIN = FXTI / IDF
If register bit PLLCFG0.FRAC_CTRL = 1
FVCO = FINFIN * (LDF + FRACT/2
16 + 1/217)
FPHI = FVCO / ODF
When register bit PLLCFG0.DITHER_DISABLE[1] = 1, the 1/217 factor is not in the
multiplication. This is recommended in order to keep register bit
PLLCFG0.DITHER_DISABLE[1] = 0, otherwise there can be spurious signals in the output
clock spectrum.
C2
R1
C1
Vc
Ground



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