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LSM6DSV80X データシート(PDF) 17 Page - STMicroelectronics |
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LSM6DSV80X データシート(HTML) 17 Page - STMicroelectronics |
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17 / 181 page ![]() 4.4 Communication interface characteristics 4.4.1 SPI - serial peripheral interface Subject to general operating conditions for VDD and Top. @VDDIO = 1.8 V, T = 25°C unless otherwise noted. Table 6. SPI target timing values (VDDIO at 1.8 V) Symbol Parameter Value(1) Unit Min Typ Max fc(SPC) SPI clock frequency 10 MHz tc(SPC) SPI clock period 100 ns thigh(SPC) SPI clock high period 45 tlow(SPC) SPI clock low period 45 tsu(CS) CS setup time (mode 3) 5 CS setup time (mode 0) 20 th(CS) CS hold time (mode 3) 20 CS hold time (mode 0) 20 tsu(SI) SDI input setup time 5 th(SI) SDI input hold time 15 tv(SO) SDO valid output time 15 25 tdis(SO) SDO output disable time 50 Cload Bus capacitance 100 pF 1. Values are evaluated at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production. Subject to general operating conditions for VDD and Top. @VDDIO = 1.2 V, T = 25°C unless otherwise noted. Table 7. SPI target timing values (VDDIO at 1.2 V) Symbol Parameter Value(1) Unit Min Typ Max fc(SPC) SPI clock frequency 10 MHz tc(SPC) SPI clock period 100 ns thigh(SPC) SPI clock high period 45 tlow(SPC) SPI clock low period 45 tsu(CS) CS setup time (mode 3) 25 CS setup time (mode 0) 50 th(CS) CS hold time (mode 3) 50 CS hold time (mode 0) 50 tsu(SI) SDI input setup time 15 th(SI) SDI input hold time 30 tv(SO) SDO valid output time 30 tdis(SO) SDO output disable time 50 Cload Bus capacitance 50 pF 1. Values are evaluated at 10 MHz clock frequency for SPI with both 4 and 3 wires, based on characterization results, not tested in production. LSM6DSV80X Module specifications DS14764 - Rev 1 page 17/181 |
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