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ST10F271 データシート(PDF) 142 Page - STMicroelectronics |
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ST10F271 データシート(HTML) 142 Page - STMicroelectronics |
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142 / 173 page  Electrical characteristics ST10F271 142/173 Figure 45. Generation mechanisms for the CPU clock 24.8.3 Clock generation modes Next Table 68 associates the combinations of these three bits with the respective clock generation mode. 1. The external clock input range refers to a CPU clock range of 1...64 MHz. Besides, the PLL usage is limited to 4-8MHz. All configurations need a crystal (or ceramic resonator) to generate the CPU clock through the internal oscillator amplifier (apart from Direct Drive): vice versa, the clock can be forced through an external clock source only in Direct Drive mode (on-chip oscillator amplifier disabled, so no crystal or resonator can be used). 2. The maximum depends on the duty cycle of the external clock signal: when 64MHz is used, 50% duty cycle shall be granted (low phase = high phase = 7.8ns); when 32MHz is selected a 25% duty cycle can be accepted (minimum phase, high or low, again equal to 7.8ns). 3. The limits on input frequency are 4-8MHz since the usage of the internal oscillator amplifier is required. Also when the PLL is not used and the CPU clock corresponds to FXTAL/2, an external crystal or resonator shall be used: it is not possible to force any clock though an external clock source. TCLTCL TCLTCL fCPU fXTAL fCPU fXTAL Phase locked loop operation Direct Clock Drive TCL TCL fCPU fXTAL Prescaler Operation Table 68. On-chip clock generator selections P0.15-13 (P0H.7-5) CPU Frequency fCPU = fXTAL x F External Clock Input Range 1) 3) Notes 11 1 FXTAL x 4 4 to 8MHz Default configuration 11 0 FXTAL x 3 5.3 to 8MHz See Table 69 10 1 FXTAL x 8 4 to 8MHz 10 0 FXTAL x 5 6.4 to 8MHz 01 1 FXTAL x 1 1 to 64MHz Direct Drive (oscillator bypassed) 2) 01 0 FXTAL x 10 4 to 6.4MHz 00 1 FXTAL / 2 4 to 8MHz CPU clock via prescaler 3) 00 0 FXTAL x 16 4MHz |
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