L6740L datasheet(39/44 Pages) STMICROELECTRONICS

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L6740L

LTB technology™

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LTB technology™

LTB Technology™ further enhances the performances of Dual-Edge Asynchronous

Systems by reducing the system latencies and immediately turning ON all the phases to

provide the correct amount of energy to the load. By properly designing the LTB network as

well as the LTB Gain, the undershoot and the ring-back can be minimized also optimizing

the output capacitors count. LTB Technology™ applies only to the CORE Section.

LTB Technology™ monitors the output voltage through a dedicated pin detecting Load-

Transients with selected dV/dt, it cancels the interleaved phase-shift, turning-on

simultaneously all phases. it then implements a parallel, independent loop that reacts to

Load-Transients bypassing E/A latencies.

LTB Technology™ Control Loop is reported in Figure 18.

Figure 18.

LTB technology™ control loop (CORE section).

The LTB detector is able to detect output load transients by coupling the output voltage

through an RLTB - CLTB network. After detecting a load transient, the LTB Ramp is reset and

then compared with the COMP pin level. The resulting duty-cycle programmed is then OR-

ed with the PWMx signal of each phase by-passing the main control loop. All the phases will

then be turned-on together and the EA latencies results bypassed as well.

Sensitivity of the Load Transient Detector and the Gain of the LTB Ramp can be

programmed in order to control precisely both the undershoot and the ring-back.

●

Detector Design. RLTB - CLTB is design according to the output voltage deviation dVOUT

which is desired the controller to be sensitive as follow:

Ref

COMP

VSEN

DROOP

PWM

L/N

ESR

d VCOMP

VOUT

ZF(s)

ZFB(s)

VID

Monitor

RLTB

CLTB

PWM_BOOST

LTB Ramp

LTB

LT Detect

LTB

OUT

µA

------------------

LTB

π NR

LTB

⋅⋅

⋅

--------------------------------------------------

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