データシートサーチシステム
  Japanese  ▼
ALLDATASHEET.JP

X  

ADRF5030BCCZN-R7 データシート(PDF) 7 Page - Analog Devices

部品番号 ADRF5030BCCZN-R7
部品情報  100 MHz to 20 GHz, Non-Reflective, Silicon SPDT Switch
PDF  13 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

ADRF5030BCCZN-R7 データシート(HTML) 7 Page - Analog Devices

Back Button ADRF5030BCCZN-R7 Datasheet HTML 3Page - Analog Devices ADRF5030BCCZN-R7 Datasheet HTML 4Page - Analog Devices ADRF5030BCCZN-R7 Datasheet HTML 5Page - Analog Devices ADRF5030BCCZN-R7 Datasheet HTML 6Page - Analog Devices ADRF5030BCCZN-R7 Datasheet HTML 7Page - Analog Devices ADRF5030BCCZN-R7 Datasheet HTML 8Page - Analog Devices ADRF5030BCCZN-R7 Datasheet HTML 9Page - Analog Devices ADRF5030BCCZN-R7 Datasheet HTML 10Page - Analog Devices ADRF5030BCCZN-R7 Datasheet HTML 11Page - Analog Devices Next Button
Zoom Inzoom in Zoom Outzoom out
 7 / 13 page
background image
Data Sheet
ADRF5030
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
analog.com
Rev. 0 | 7 of 13
Figure 3. Pin Configuration (Top View)
Table 6. Pin Function Descriptions
Pin No.
Mnemonic
Description
1, 2, 4, 5, 6, 7, 9, 10, 13, 16, 17,
19, 20
GND
Ground. These pins must be connected to the RF/DC ground of the PCB.
3
RFC
RF Common Port. This pin is DC-coupled to 0 V. No DC-blocking capacitor is necessary when the RF line potential is equal
to 0 V DC. See Figure 4 for the interface schematic.
8
RF1
RF Port 1. This pin is DC-coupled to 0 V. No DC-blocking capacitor is necessary when the RF line potential is equal to 0 V
DC. See Figure 4 for the interface schematic.
11
VDD
Positive Supply Voltage. See Figure 6 for the interface schematic.
12
CTRL
Control Input Voltage. See for the truth table. See Figure 5 for the interface schematic.
14
EN
Enable Input Voltage. See for the truth table. See Figure 5 for the interface schematic.
15
VSS
Negative Supply Voltage. See Figure 7 for the interface schematic.
18
RF2
RF Port 2. This pin is DC-coupled to 0 V. No DC-blocking capacitor is necessary when the RF line potential is equal to 0 V
DC. See Figure 4 for the interface schematic
EPAD
Exposed Pad. The exposed pad must be connected to the RF/DC ground of the PCB.



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13


データシート ダウンロード

Go To PDF Page


リンク URL



ALLDATASHEETはお客様のビジネスに役立ちますか?  [ DONATE ] 

Alldatasheetは   |   広告   |   お問い合わせ   |   プライバシーポリシー   |   データシートへのリンク    |   リンク交換   |   メーカーリスト
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com