Data Sheet

AD4052/AD4058

REGISTER DETAILS

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Rev. B | 62 of 66

Table 44. Bit Descriptions for TIMER_CONFIG (Continued)

Bits

Bit Name

Description

Reset

Access

0x4: 30 µs.

0x5: 100 µs.

0x6: 330 µs.

0x7: 1 ms.

0x8: 2 ms.

0x9: 3 ms.

0xA: 4 ms.

0xB: 5 ms.

0xC: 6 ms.

0xD: 7 ms.

0xE: 8 ms.

0xF: 9 ms.

1 NOTE that the 2 MSPS and 1 MSPS settings are invalid for the AD4058. On the AD4058, the FS_BURST_AUTO register must be updated accordingly before entering the

burst averaging mode or the autonomous modes.

MAXIMUM THRESHOLD CONFIGURATION REGISTER

Address: 0x28 to 0x29, Reset: 0x0000, Name: MAX_LIMIT_REG

Table 45. Bit Descriptions for MAX_LIMIT_REG

Bits

Bit Name

Description

Reset

Access

[15:12]

RESERVED

Reserved.

0x0

R

[11:0]

MAX_LIMIT

Maximum Threshold Limit Setting. Sets the maximum threshold limit for autonomous modes. Uses

the same data format (twos complement or straight binary) as the ADC as set by the DATA_FORMAT

bit.

0x0

R/W

MINIMUM THRESHOLD CONFIGURATION REGISTER

Address: 0x2A to 0x2B, Reset: 0x0000, Name: MIN_LIMIT_REG

Table 46. Bit Descriptions for MIN_LIMIT_REG

Bits

Bit Name

Description

Reset

Access

[15:12]

RESERVED

Reserved.

0x0

R

[11:0]

MIN_LIMIT

Minimum Threshold Limit Setting. Sets the minimum threshold limit for autonomous modes. Uses the

same data format (twos complement or straight binary) as the ADC as set by the DATA_FORMAT bit.

0x0

R/W

MAXIMUM THRESHOLD HYSTERESIS REGISTER

Address: 0x2C, Reset: 0x00, Name: MAX_HYST_REG