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AX88796BLF データシート(PDF) 71 Page - ASIX Electronics Corporation

部品番号 AX88796BLF
部品情報  Low-pin-count Non-PCI 8/16-bit 10/100M Fast Ethernet Controller
PDF  82 Pages
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メーカー  ASIX [ASIX Electronics Corporation]
ホームページ  http://www.asix.com.tw
Logo ASIX - ASIX Electronics Corporation

AX88796BLF データシート(HTML) 71 Page - ASIX Electronics Corporation

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ASIX ELECTRONICS CORPORATION
71
AX88796BLF / AX88796BLI
7.4.5 Burst Reads Access Timing
Burst read access is enabled when set FIFO_SEL(SA5) is driven high during a read access. This is normally
accomplished by connecting the FIFO_SEL(SA5) signal to a high-order address line. This mode is useful when
the host processor must increment its address when accessing the AX88796B.
In this mode, performance is improved by allowing an unlimited number of back-to-back WORDS read cycles.
AX88796B base on SA0 or SA1 address toggles to identify WORD access cycle time. Host can set burst cycle
base on SA0 or SA1 toggle by BCB1 (CR page3 Offset 0Dh).
Tdoff
Tdoh
Tadv
Tadv
Tadv
Tdv
Tdon
Trdh
Trdh
Tah
Tas u
Tacyc
Tacyc
Tacy c
Tacy c
Tacyc
Tacyc
FIFO_SEL(SA5)
SA1 or SA0
CSn, RDn
SD[15:0]
Symbol
Description
Min
Typ.
Max
Units
Tasu
ADDRESS SETUP TIME
0
-
-
ns
Tah
ADDRESS HOLD TIME
0
-
-
ns
Tdv
DATA VALID TIME FROM RDn
-
-
33*
1
35*
2
ns
Tadv
DATA VALID TIME FROM ADDRESS
33*
1
35*
2
ns
Tdoh
DATA OUTPUT HOLD TIME
0
-
-
ns
Trdh
RDn HI REQUIRE TIME
13
-
-
ns
Tacyc
READ CYCLE TIME
48
ns
Tdon
DATA BUFFER TURN ON
0
ns
Tdoff
DATA BUFFER TURN OFF
7
ns
*
1 : Base on SD bus output load 25pF
*
2 : Base on SD bus output load 50pF



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