TC9256, 57APG/AFG

2006-07-14

7

Serial Transfer Format

The serial transfer format consists of 8 address bits and 24 data bits (Figure 1). Addresses D0H to D3H are

used.

• Serial data transfer

Serial data are transferred in sync with the clock signal. In the idle state, the PERIOD, CLOCK and DATA

pin lines are all set to “H” level. When the period signal is at “L” level, serial data transfer starts at the falling

edge of the clock signal. Data transfer ends when the period signal is set to “L” level while the clock signal is

at “H” level. Once serial data transfer has begun, however, no more than 8 falls of the clock signal can occur

during the time the period signal is at “L” level.

Since the receiving side receives the serial data as valid data at the rising edge of the clock signal, it is

effective for the sending side to produce output in sync with the falling edge of the clock signal.

To receive serial data from the output registers (D1H, D3H), set the serial data output to high impedance

after the 8-bit address is output but before the next falling edge of the clock signal.

Data reception subsequently continues until the period signal becomes “L” level; data transfer ends just

before the rising edge of the period signal. Therefore, the data pin must have an open-drain or tristate

interface.

Note 1: When power is turned on, some internal circuits have undefined states. To set the internal circuit state,

execute a dummy data transfer before performing regular data transfer.

Note 2: Times t1 to t8 have the following values:

t1 >

= 1.0 µs

t2 >

= 1.0 µs

t3 >

= 0.3 µs

t4 >

= 0.3 µs

t5 >

= 0.3 µs

t6 >

= 1.0 µs

t7 >

= 1.0 µs

t8 >

= 0.3 µs

Note 3: Asterisks represent numbers taken from addresses, as in D*H.

Figure 1