AMC80

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SBOS559B – MAY 2011 – REVISED OCTOBER 2015

Feature Description (continued)

both hardware interrupt outputs.

•

Fan Divisor/RST_OUT/OS Register: Bits 0 to 5 of this register contain the divisor bits for the FAN1 and

FAN2 inputs. Bits 6 and 7 control the function of the RST_OUT/OS output.

•

OS Configuration/Temperature Resolution Register: The configuration of the overtemperature shutdown

(OS) is controlled by the lower three bits of this register. Bit 3 enables 12-bit temperature conversions. In 12-

bit mode, bits 4 to 7 represent the four LSBs of the temperature measurement. In 9-bit mode, bit 4 represents

the LSB of the temperature measurement.

•

Conversion Rate Register: Sets the time interval of the continuous monitoring cycle to either fixed or

programmable (see the Conversion Rate Count Register for setting the programmable time interval).

•

Voltage/Temperature Channel Disable Register: Allows voltage inputs and the local temperature

conversion to be disabled.

•

Input Mode Register: Allows voltage inputs to be configured as single-ended or as a differential pair with

normal or reverse polarity.

•

ADC Control Register: Bits 0 to 2 set the programmable conversion rate for the 10-bit ADC. Bits 3 to 5 allow

for programmable input full-scale voltage.

•

Conversion Rate Count Register: Selects the adjustable time interval when the conversion rate of the

continuous monitoring cycle is set to programmable.

•

Value RAM: The monitoring results (for temperature, voltages, fan counts, and Fan Divisor/RST_OUT/OS

Register limits) are all contained in the Value RAM. The Value RAM consists of 32 bytes. The first 10 bytes

are all of the results, the next 20 bytes are the interrupt alarm limits, and the last two bytes are at the upper

locations for manufacturer ID and die revision ID.

The AMC80 SMBus is compatible with both fast mode (400 kHz) and high-speed mode (3.4 MHz) two-wire

interface modes of operation. The AMC80 supports a timeout reset function on SDA and SCL that prevents two-

wire bus lockup, and includes an analog filter on the two-wire digital control lines that improves noise immunity.

Three address pins (A0 to A2), allow up to eight devices on a single bus. When enabled, the AMC80 starts by

cycling through each measurement in sequence, and continuously loops through the sequence based on the

Conversion Rate Register (address 07h) setting. Each measured value is compared to values stored in the Value

RAM Registers (addresses 2Ah to 3Dh). When the measured value exceeds the programmed limit, the AMC80

sets a corresponding interrupt in the Interrupt Status Registers (addresses 01h and 02h). Two output interrupt

lines (INT and RST_OUT/OS) are available. INT is fully programmable with the ability to mask each interrupt

source and each output. The Fan Divisor/RST_OUT/OS Register (address 05h) has control bits that enable or

disable the hardware interrupts. Additional digital inputs are provided for daisy-chaining the interrupt output pin,

INT. This configuration is achieved by connecting multiple external temperature sensors (for example, the

TMP75) to the board temperature interrupt (BTI) input and/or the GPI/CI input. The chassis intrusion (CI) input is

designed to accept an active high signal from an external circuit that latches (for example, when the chassis from

a server rack is removed).

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