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AT42QT1060 [DATASHEET]

9505H–AT42–04/2015

4.

I2C Communications

4.1

I2C Protocol

4.1.1

Protocol

The I2C protocol is based around access to an address table (see Table 5-1 on page 16) and supports multibyte

reads and writes. The maximum clock rate is 100 kHz.

4.1.2

Signals

The I2C interface requires two signals to operate:



SDA - Serial Data



SCL - Serial Clock

A third line, CHG, is used to signal when the device has seen a change in the status byte:



CHG: Open-drain, active low when any capacitive key in the key mask has changed state or any input line has

changed state since the last I2C read. After reading the two status bytes, this pin floats (high) again if it is

pulled up with an external resistor. If the status bytes change back to their original state before the host has

read the status bytes (for example, a touch followed by a release), the CHG line will be held low. In this case,

a read to any memory location will clear the CHG line.

4.1.3

Clock Stretching

The device has an internal monitor that resets its I2C hardware if either I2C-compatible line is held low, without the

other line changing, for more than about 14 ms. It is important that no other device on the bus clock stretches for

14 ms, otherwise the monitor will reset the I

2C hardware and transfers with the chip may be corrupted.

If the device is configured to run in stand-alone mode, the monitor will be turned off.

4.2

I2C Address

There is one preset I2C address of

0x12. This is not changeable.