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CDCS503 データシート(PDF) 5 Page - Texas Instruments

部品番号 CDCS503
部品情報  Clock Buffer/Clock Multiplier With Optional SSC
PDF  12 Pages
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メーカー  TI2 [Texas Instruments]
ホームページ  https://www.ti.com
Logo TI2 - Texas Instruments

CDCS503 データシート(HTML) 5 Page - Texas Instruments

  CDCS503 Datasheet HTML 1Page - Texas Instruments CDCS503 Datasheet HTML 2Page - Texas Instruments CDCS503 Datasheet HTML 3Page - Texas Instruments CDCS503 Datasheet HTML 4Page - Texas Instruments CDCS503 Datasheet HTML 5Page - Texas Instruments CDCS503 Datasheet HTML 6Page - Texas Instruments CDCS503 Datasheet HTML 7Page - Texas Instruments CDCS503 Datasheet HTML 8Page - Texas Instruments CDCS503 Datasheet HTML 9Page - Texas Instruments Next Button
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APPLICATION INFORMATION
SSC MODULATION
PARAMETER MEASUREMENT INFORMATION
VDD
1kW
CDCS503
LVCMOS
1kW
10pF
LVCMOS
LVCMOS
CDCS503
TypicalDriver
Impedance
~32 W
Series Termination
~18 W
Z =50
L
W
CDCS503
www.ti.com .................................................................................................................................................................................................. SCAS872 – MARCH 2009
The exact implementation of the SSC modulation plays a vital role for the EMI reduction. The CDCS503 uses a
triangular modulation scheme implemented in a way that the modulation frequency depends on the VCO
frequency of the internal PLL and the spread amount is independent from the VCO frequency.
The modulation frequency can be calculated by using one of the below formulas chosen by frequency
multiplication mode.
FS = 0: fmod = fIN / 708
FS = 1: fmod = fIN / 620
Figure 2. Test Load
Figure 3. Load for 50-
Ω Board Environment
Copyright © 2009, Texas Instruments Incorporated
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