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SC4524ASETRT データシート(PDF) 14 Page - Semtech Corporation

部品番号 SC4524ASETRT
部品情報  28V 2A Step-Down Switching Regulator
PDF  18 Pages
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メーカー  SEMTECH [Semtech Corporation]
ホームページ  http://www.semtech.com
Logo SEMTECH - Semtech Corporation

SC4524ASETRT データシート(HTML) 14 Page - Semtech Corporation

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(3) Place the compensator zero, F
Z, between 0% and
20% of the crossover frequency, F
C.
(4) Use the compensator pole, F
P, to cancel the ESR zero,
F
Z.
(5) Then, the parameters of the compensation network
can be calculated by
where g
m=0.28mA/V is the EA gain of the SC4524A.
Example: Determine the voltage compensator for an
800kHz, 2V to 3.3V/2A converter with 22uF ceramic
output capacitor.
Choose a loop gain crossover frequency of 80kHz, and
place voltage compensator zero and pole at F
Z=6kHz
(20% of F
C), and FP=600kHz. From Equation (9), the
required compensator gain at F
C is
Then the compensator parameters are
Select R
7=22.k, C5=0.47nF, and C8=0pF for the design.
Compensator parameters for various typical applications
are listed in Table 4. A MathCAD program is also available
upon request for detailed calculation of the compensator
parameters.
PCB Layout Considerations
In a step-down switching regulator, the input bypass
CESAT
D
IN
D
O
V
V
V
V
V
D
−
+
+
=
−
=
1
V
0
.
1
V
R
R
O
6
4
1
SW
D
O
L
L
F
)
D
1
(
)
V
V
(
I
⋅
−
⋅
+
=
D
SW
O
D
O
1
F
I
%
20
)
D
1
(
)
V
V
(
L
⋅
⋅
−
⋅
+
=
)
D
1
(
D
I
I
O
CIN
_
RMS
−
⋅
⋅
=


⋅
⋅
+
⋅
D
=
D
O
SW
L
O
C
F
8
1
ESR
I
V
SW
IN
O
IN
F
V
4
I
C
⋅
D
⋅
>
,
R
G
R
G
S
CA
PWM
⋅
≈
)
/
s
Q
/
s
1
()
/
s
1
(
)
C
R
s
1
(
G
V
V
2
n
2
n
p
O
ESR
PWM
c
o
ω
+
ω
+
ω
+
+
=
7
1
Z
5
R
F
2
1
C
π
=
7
1
P
8
R
F
2
1
C
π
=
,
C
R
1
O
p ≈
ω
,
C
R
1
O
ESR
Z =
ω
k
3
.
22
10
28
.
0
10
R
3
7
20
9
.
15
=
⋅
=
−
nF
45
.
0
10
1
.
22
10
16
2
1
C
3
3
5
=
⋅
⋅
⋅
⋅
π
=
pF
12
10
1
.
22
10
600
2
1
C
3
3
8
=
⋅
⋅
⋅
⋅
π
=


⋅
π
⋅
⋅
−
=
O
FB
O
C
S
CA
C
V
V
C
F
2
1
R
G
1
log
20
A
dB
9
.
15
3
.
3
0
.
1
10
22
10
80
2
1
10
1
.
6
28
1
log
20
A
6
3
3
C
=
⋅
⋅
⋅
⋅
⋅
π
⋅
⋅
⋅
⋅
−
=
−
−
m
7
g
10
R
20
C
A
=
CESAT
D
IN
D
O
V
V
V
V
V
D
−
+
+
=
−
=
1
V
0
.
1
V
R
R
O
6
4
1
SW
D
O
L
L
F
)
D
1
(
)
V
V
(
I
⋅
−
⋅
+
=
D
SW
O
D
O
1
F
I
%
20
)
D
1
(
)
V
V
(
L
⋅
⋅
−
⋅
+
=
)
D
1
(
D
I
I
O
CIN
_
RMS
−
⋅
⋅
=


⋅
⋅
+
⋅
D
=
D
O
SW
L
O
C
F
8
1
ESR
I
V
SW
IN
O
IN
F
V
4
I
C
⋅
D
⋅
>
,
R
G
R
G
S
CA
PWM
⋅
≈
)
/
s
Q
/
s
1
()
/
s
1
(
)
C
R
s
1
(
G
V
V
2
n
2
n
p
O
ESR
PWM
c
o
ω
+
ω
+
ω
+
+
=
7
1
Z
5
R
F
2
1
C
π
=
7
1
P
8
R
F
2
1
C
π
=
,
C
R
1
O
p ≈
ω
,
C
R
1
O
ESR
Z =
ω
k
3
.
22
10
28
.
0
10
R
3
7
20
9
.
15
=
⋅
=
−
nF
45
.
0
10
1
.
22
10
16
2
1
C
3
3
5
=
⋅
⋅
⋅
⋅
π
=
pF
12
10
1
.
22
10
600
2
1
C
3
3
8
=
⋅
⋅
⋅
⋅
π
=


⋅
π
⋅
⋅
−
=
O
FB
O
C
S
CA
C
V
V
C
F
2
1
R
G
1
log
20
A
dB
9
.
15
3
.
3
0
.
1
10
22
10
80
2
1
10
1
.
6
28
1
log
20
A
6
3
3
C
=
⋅
⋅
⋅
⋅
⋅
π
⋅
⋅
⋅
⋅
−
=
−
−
m
7
g
10
R
20
C
A
=
CESAT
D
IN
D
O
V
V
V
V
V
D
−
+
+
=
−
=
1
V
0
.
1
V
R
R
O
6
4
1
SW
D
O
L
L
F
)
D
1
(
)
V
V
(
I
⋅
−
⋅
+
=
D
SW
O
D
O
1
F
I
%
20
)
D
1
(
)
V
V
(
L
⋅
⋅
−
⋅
+
=
)
D
1
(
D
I
I
O
CIN
_
RMS
−
⋅
⋅
=


⋅
⋅
+
⋅
D
=
D
O
SW
L
O
C
F
8
1
ESR
I
V
SW
IN
O
IN
F
V
4
I
C
⋅
D
⋅
>
,
R
G
R
G
S
CA
PWM
⋅
≈
)
/
s
Q
/
s
1
()
/
s
1
(
)
C
R
s
1
(
G
V
V
2
n
2
n
p
O
ESR
PWM
c
o
ω
+
ω
+
ω
+
+
=
7
1
Z
5
R
F
2
1
C
π
=
7
1
P
8
R
F
2
1
C
π
=
,
C
R
1
O
p ≈
ω
,
C
R
1
O
ESR
Z =
ω
k
3
.
22
10
28
.
0
10
R
3
7
20
9
.
15
=
⋅
=
−
nF
45
.
0
10
1
.
22
10
16
2
1
C
3
3
5
=
⋅
⋅
⋅
⋅
π
=
pF
12
10
1
.
22
10
600
2
1
C
3
3
8
=
⋅
⋅
⋅
⋅
π
=


⋅
π
⋅
⋅
−
=
O
FB
O
C
S
CA
C
V
V
C
F
2
1
R
G
1
log
20
A
dB
9
.
15
3
.
3
0
.
1
10
22
10
80
2
1
10
1
.
6
28
1
log
20
A
6
3
3
C
=
⋅
⋅
⋅
⋅
⋅
π
⋅
⋅
⋅
⋅
−
=
−
−
m
7
g
10
R
20
C
A
=
CESAT
D
IN
D
O
V
V
V
V
V
D
−
+
+
=
−
=
1
V
0
.
1
V
R
R
O
6
4
1
SW
D
O
L
L
F
)
D
1
(
)
V
V
(
I
⋅
−
⋅
+
=
D
SW
O
D
O
1
F
I
%
20
)
D
1
(
)
V
V
(
L
⋅
⋅
−
⋅
+
=
)
D
1
(
D
I
I
O
CIN
_
RMS
−
⋅
⋅
=


⋅
⋅
+
⋅
D
=
D
O
SW
L
O
C
F
8
1
ESR
I
V
SW
IN
O
IN
F
V
4
I
C
⋅
D
⋅
>
,
R
G
R
G
S
CA
PWM
⋅
≈
)
/
s
Q
/
s
1
()
/
s
1
(
)
C
R
s
1
(
G
V
V
2
n
2
n
p
O
ESR
PWM
c
o
ω
+
ω
+
ω
+
+
=
7
1
Z
5
R
F
2
1
C
π
=
7
1
P
8
R
F
2
1
C
π
=
,
C
R
1
O
p ≈
ω
,
C
R
1
O
ESR
Z =
ω
k
3
.
22
10
28
.
0
10
R
3
7
20
9
.
15
=
⋅
=
−
nF
45
.
0
10
1
.
22
10
16
2
1
C
3
3
5
=
⋅
⋅
⋅
⋅
π
=
pF
12
10
1
.
22
10
600
2
1
C
3
3
8
=
⋅
⋅
⋅
⋅
π
=


⋅
π
⋅
⋅
−
=
O
FB
O
C
S
CA
C
V
V
C
F
2
1
R
G
1
log
20
A
dB
9
.
15
3
.
3
0
.
1
10
22
10
80
2
1
10
1
.
6
28
1
log
20
A
6
3
3
C
=
⋅
⋅
⋅
⋅
⋅
π
⋅
⋅
⋅
⋅
−
=
−
−
m
7
g
10
R
20
C
A
=
CESAT
D
IN
D
O
V
V
V
V
V
D
−
+
+
=
−
=
1
V
0
.
1
V
R
R
O
6
4
1
SW
D
O
L
L
F
)
D
1
(
)
V
V
(
I
⋅
−
⋅
+
=
D
SW
O
D
O
1
F
I
%
20
)
D
1
(
)
V
V
(
L
⋅
⋅
−
⋅
+
=
)
D
1
(
D
I
I
O
CIN
_
RMS
−
⋅
⋅
=


⋅
⋅
+
⋅
D
=
D
O
SW
L
O
C
F
8
1
ESR
I
V
SW
IN
O
IN
F
V
4
I
C
⋅
D
⋅
>
,
R
G
R
G
S
CA
PWM
⋅
≈
)
/
s
Q
/
s
1
()
/
s
1
(
)
C
R
s
1
(
G
V
V
2
n
2
n
p
O
ESR
PWM
c
o
ω
+
ω
+
ω
+
+
=
7
1
Z
5
R
F
2
1
C
π
=
7
1
P
8
R
F
2
1
C
π
=
,
C
R
1
O
p ≈
ω
,
C
R
1
O
ESR
Z =
ω
k
3
.
22
10
28
.
0
10
R
3
7
20
9
.
15
=
⋅
=
−
nF
45
.
0
10
1
.
22
10
16
2
1
C
3
3
5
=
⋅
⋅
⋅
⋅
π
=
pF
12
10
1
.
22
10
600
2
1
C
3
3
8
=
⋅
⋅
⋅
⋅
π
=


⋅
π
⋅
⋅
−
=
O
FB
O
C
S
CA
C
V
V
C
F
2
1
R
G
1
log
20
A
dB
9
.
15
3
.
3
0
.
1
10
22
10
80
2
1
10
1
.
6
28
1
log
20
A
6
3
3
C
=
⋅
⋅
⋅
⋅
⋅
π
⋅
⋅
⋅
⋅
−
=
−
−
m
7
g
10
R
20
C
A
=
CESAT
D
IN
D
O
V
V
V
V
V
D
−
+
+
=
−
=
1
V
0
.
1
V
R
R
O
6
4
1
SW
D
O
L
L
F
)
D
1
(
)
V
V
(
I
⋅
−
⋅
+
=
D
SW
O
D
O
1
F
I
%
20
)
D
1
(
)
V
V
(
L
⋅
⋅
−
⋅
+
=
)
D
1
(
D
I
I
O
CIN
_
RMS
−
⋅
⋅
=


⋅
⋅
+
⋅
D
=
D
O
SW
L
O
C
F
8
1
ESR
I
V
SW
IN
O
IN
F
V
4
I
C
⋅
D
⋅
>
,
R
G
R
G
S
CA
PWM
⋅
≈
)
/
s
Q
/
s
1
()
/
s
1
(
)
C
R
s
1
(
G
V
V
2
n
2
n
p
O
ESR
PWM
c
o
ω
+
ω
+
ω
+
+
=
7
1
Z
5
R
F
2
1
C
π
=
7
1
P
8
R
F
2
1
C
π
=
,
C
R
1
O
p ≈
ω
,
C
R
1
O
ESR
Z =
ω
k
3
.
22
10
28
.
0
10
R
3
7
20
9
.
15
=
⋅
=
−
nF
45
.
0
10
1
.
22
10
16
2
1
C
3
3
5
=
⋅
⋅
⋅
⋅
π
=
pF
12
10
1
.
22
10
600
2
1
C
3
3
8
=
⋅
⋅
⋅
⋅
π
=


⋅
π
⋅
⋅
−
=
O
FB
O
C
S
CA
C
V
V
C
F
2
1
R
G
1
log
20
A
dB
9
.
15
3
.
3
0
.
1
10
22
10
80
2
1
10
1
.
6
28
1
log
20
A
6
3
3
C
=
⋅
⋅
⋅
⋅
⋅
π
⋅
⋅
⋅
⋅
−
=
−
−
m
7
g
10
R
20
C
A
=
capacitor, the main power switch and the freewheeling
diode carry pulse current (Figure 9). For jitter-free
operation,thesizeoftheloopformedbythesecomponents
should be minimized. Since the power switch is already
integrated within the SC4524A, connecting the anode of
the freewheeling diode close to the negative terminal of
the input bypass capacitor minimizes size of the switched
current loop. The input bypass capacitor should be placed
close to the IN pin. Shortening the traces of the SW and
BST nodes reduces the parasitic trace inductance at these
nodes. This not only reduces EMI but also decreases
switching voltage spikes at these nodes.
The exposed pad should be soldered to a large ground
plane as the ground copper acts as a heat sink for the
device. To ensure proper adhesion to the ground plane,
avoid using vias directly under the device.
Figure 9. Heavy lines indicate the critical pulse
current loop. The inductance of this
loop should be minimized.
Vout
Vin
+
+
Currents in Power Section
IN
V
OUT
V
L
Z
Vout
Vin
+
+
Currents in Power Section
IN
V
OUT
V
L
Z
SC4524A
4
Applications Information (Cont.)



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