PCI Bus

Freescale Semiconductor

21

Figure 17. DDR Read Timing

10

PCI Bus

The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please

refer to the PCI 2.2 spec for a more detailed timing analysis.

Table 14. PCI Timing Specifications

Num

Characteristic

Min

Max

Unit

Notes

Frequency of Operation

25

50

MHz

1

P1

40

ns

2

P2

Address, Data, and Command (33

< PCI ≤ 50 Mhz)—Input Setup (t

—

ns

P3

Address, Data, and Command (0

< PCI ≤ 33 Mhz)—Input Setup (t

—

ns

P4

6.0

ns

3

P5

—

11.0

ns

P6

—

ns

4

SDCLK0

SDCLK1

SDCSn,SDWE,

SDDQS

SDDATA

SDADDR,

RAS, CAS

SDBA[1:0]

CMD

ROW

DD1

DD5

DD4

WD1 WD2 WD3 WD4

SDDQS

DD9

SDCLK0

SDCLK1

DD3

DD2

SDDATA

WD1 WD2 WD3 WD4

DD10

CL=2

CL=2.5

COL

DQS Read

Preamble

DQS Read

Postamble

DQS Read

Preamble

DQS Read

Postamble