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ADS5271 データシート(PDF) 28 Page - Texas Instruments |
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ADS5271 データシート(HTML) 28 Page - Texas Instruments |
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28 / 42 page ![]() 90 85 80 75 70 65 60 55 ClockDutyCycle(%) 35 65 50 45 40 55 SNR(dBFS) SFDR(dBc) f =65MHz f =10MHz S IN 60 95 85 80 75 70 60 ClockDutyCycle(%) 20 80 50 40 30 60 SNR(dBFS) SFDR(dBc) f =65MHz f =10MHz S IN 90 70 65 90 85 80 75 70 65 60 ExternalReferenceCommon-ModeVoltage,(REF +REF )/2(V) T B 1.35 1.65 1.50 1.45 1.40 SNR(dBFS) SFDR(dBc) f =65MHz f =10MHz S IN 1.55 1.60 Externalreferencedifferentialvoltagemaintainedat2V. 90 85 80 75 70 65 60 VoltageonV (V) CM 1.35 1.65 1.50 1.45 1.40 SNR(dBFS) SFDR(dBc) f =65MHz f =10MHz S IN 1.55 1.60 ADS5287 SBAS428D – JANUARY 2008 – REVISED JUNE 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) Typical values at +25°C. Minimum and maximum values are measured across the specified temperature range of TMIN = –40°C to TMAX = +85°C, AVDD = 3.3V, LVDD = 1.8V, clock frequency = 10MSPS to 65MSPS, 50% clock duty cycle, –1dBFS differential analog input, internal reference mode, ISET resistor = 56.2kΩ, and LVDS buffer current setting = 3.5mA, unless otherwise noted.Typical values at +25°C. DYNAMIC PERFORMANCE DYNAMIC PERFORMANCE vs vs EXTERNAL REFERENCE COMMON-MODE VOLTAGE EXTERNAL REFERENCE FORCED THROUGH VCM Figure 20. Figure 21. DYNAMIC PERFORMANCE DYNAMIC PERFORMANCE vs vs CLOCK DUTY CYCLE CLOCK DUTY CYCLE (DCC DISABLED) (DCC ENABLED) Figure 22. Figure 23. 28 Copyright © 2008–2012, Texas Instruments Incorporated |
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