8V97052 datasheet(13/47 Pages) RENESAS

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R31DS0022EU0110 Rev.1.1

Page 13

Feb 6, 2023

8V97052 Datasheet

2.16 Phase Resync

The phase alignment function operates based on adjusting the “fractional” phase, so the phase can settle to any

one of the MOD phase offsets, MOD being the modulus of the fractional feedback divider.

The phase adjustment can provide a 0° – 360° of phase adjust, assuming that the output divider ratio is set to 1.

The phase step is TVCO/MOD for the normal case of fundamental feedback. TVCO is the period of the VCO.

The feedback select bit (FbkSel bit, Bit D23 in Register 4) gives the choices of fundamental feedback or divided

feedback. This bit controls the mux that sends the VCO signal or the output divider signal to the feedback loop.

The user can get larger phase steps in the divided mode, but the phase noise may be degraded, especially in

fractional mode. Should the user select this option, the phase adjustment step would be ~TOUT/MOD, where TOUT

is the output signal period.

When the part is in fractional mode, the device is dithering the feedback divider value. As an example, when using

a 4GHz VCO frequency, the feedback divider value may dither between div-by-20 and div-by-21. Since the period

is 250ps, there will be 250ps of jitter added to the phase detector. This jitter is filtered by the loop, but can still

show up at the output if the loop bandwidth is high. When using a divider before the feedback divider, the effective

VCO period is increased. If a div-by-64 is used for example, the period becomes

64  250ps = 16ns. This means that there could be an additional 16ns of jitter at the PFD, rather than 250ps. It is

more challenging for the loop to filter this larger amount of jitter and this will degrade the overall performance of

the part, unless the user chooses to use a very low loop bandwidth. With normal loop bandwidth configurations

(for optimal noise), the phase noise would be degraded when using a divided feedback mode.

The phase resync is controlled by setting Bits [D18:D17] in Register 7 to D18 = 1 and D17 = 0.

When phase resync is used, an internal timer generates sync signals every TSYNC where:

TSYNC = ClkDiv  MOD  TPFD

(5)

▪

ClkDiv = the value (from 1 and 4095) programmed in the 12-bit clock counter in Bits [D31:D20] in Register 4.

The 12-bit counter is used as a timer for Fast Lock and for the Phase Resync function.

▪

MOD = the modulus value (Bits [D14:D3] of Register 1 and Bits [D22:D3] of Register 5)

▪

TPFD = the PFD period

In Equation 5, the minimum of either MOD value or 4095 is used for calculating TSYNC.

Figure 8. 12-bit Counter for Fast Lock and Phase Resync

After the user program a frequency, the second sync pulse coming from the 12-bit counter, after the nCS is

asserted high, is used to resynchronize the output phase to the input phase. To ensure that the PLL is locked

before to resynchronize the output phase, TSYNC must be larger than the worst case lock time.

2.17 Fast Lock Function

The device uses a fast-lock mode to decrease lock time.

In order to allow the fast lock mode, the Fast Lock Switch (FLSW) is shorted to ground and the Charge Pump

Current (ICP) is changed temporarily until the fast lock mode is disabled.

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