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AD7984 データシート(PDF) 5 Page - Analog Devices

部品番号 AD7984
部品情報  18-Bit, 1.33 MSPS PulSAR 10.5 mW ADC in MSOP/QFN
PDF  24 Pages
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メーカー  AD [Analog Devices]
ホームページ  http://www.analog.com
Logo AD - Analog Devices

AD7984 データシート(HTML) 5 Page - Analog Devices

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AD7984
Rev. 0 | Page 5 of 24
TIMING SPECIFICATIONS
TA = −40°C to +85°C, VDD = 2.37 V to 2.63 V, VIO = 2.3 V to 5.5 V, unless otherwise noted.1
Table 4.
Parameter
Symbol
Min
Typ
Max
Unit
Conversion Time: CNV Rising Edge to Data Available
tCONV
300
500
ns
Acquisition Time
tACQ
250
ns
Time Between Conversions
tCYC
750
ns
CNV Pulse Width (CS Mode)
tCNVH
10
ns
SCK Period (CS Mode)
tSCK
VIO Above 4.5 V
10.5
ns
VIO Above 3 V
12
ns
VIO Above 2.7 V
13
ns
VIO Above 2.3 V
15
ns
SCK Period (Chain Mode)
tSCK
VIO Above 4.5 V
11.5
ns
VIO Above 3 V
13
ns
VIO Above 2.7 V
14
ns
VIO Above 2.3 V
16
ns
SCK Low Time
tSCKL
4.5
ns
SCK High Time
tSCKH
4.5
ns
SCK Falling Edge to Data Remains Valid
tHSDO
3
ns
SCK Falling Edge to Data Valid Delay
tDSDO
VIO Above 4.5 V
9.5
ns
VIO Above 3 V
11
ns
VIO Above 2.7 V
12
ns
VIO Above 2.3 V
14
ns
CNV or SDI Low to SDO D15 MSB Valid (CS Mode)
tEN
VIO Above 3 V
10
ns
VIO Above 2.3 V
15
ns
CNV or SDI High or Last SCK Falling Edge to SDO High Impedance (CS Mode)
tDIS
20
ns
SDI Valid Setup Time from CNV Rising Edge
tSSDICNV
5
ns
SDI Valid Hold Time from CNV Rising Edge (CS Mode)
tHSDICNV
2
ns
SDI Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSDICNV
0
ns
SCK Valid Setup Time from CNV Rising Edge (Chain Mode)
tSSCKCNV
5
ns
SCK Valid Hold Time from CNV Rising Edge (Chain Mode)
tHSCKCNV
5
ns
SDI Valid Setup Time from SCK Falling Edge (Chain Mode)
tSSDISCK
2
ns
SDI Valid Hold Time from SCK Falling Edge (Chain Mode)
tHSDISCK
3
ns
SDI High to SDO High (Chain Mode with Busy Indicator)
tDSDOSDI
15
ns
1 See Figure 2 and Figure 3 for load conditions.
500µA
IOL
500µA
IOH
1.4V
TO SDO
CL
20pF
Figure 2. Load Circuit for Digital Interface Timing
X% VIO1
Y% VIO1
VIH2
VIL2
VIL2
VIH2
tDELAY
tDELAY
1FOR VIO ≤ 3.0V, X = 90, AND Y = 10; FOR VIO > 3.0V, X = 70, AND Y = 30.
2MINIMUM VIH AND MAXIMUM VIL USED. SEE DIGITAL INPUTS
SPECIFICATIONS IN TABLE 3.
Figure 3. Voltage Levels for Timing



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