This X24012 device has been acquired by

IC MICROSYSTEMS from Xicor, Inc.

1

START

STOP

LOGIC

CONTROL

LOGIC

SLAVE ADDRESS

REGISTER

+COMPARATOR

H.V. GENERATION

TIMING

& CONTROL

WORD

ADDRESS

COUNTER

XDEC

YDEC

D

OUT

ACK

E

2

PROM

32 X 32

DATA REGISTER

START CYCLE

(8) V

CC

R/W

PIN

(4) V

SS

(5) SDA

(6) SCL

(3) A2

(2) A1

(1) A0

D

OUT

LOAD

INC

CK

8

DESCRIPTION

The X24012 is a CMOS 1024 bit serial E

internally organized as one 128 x 8 bank. The X24012

features a serial interface and software protocol allowing

operation on a simple two wire bus. Three address

inputs allow up to eight devices to share a common two wire

bus.

Xicor E

requiring extended endurance. Inherent data retention

is greater than 100 years. The X24012 is available in eight

pin DIP and SOIC packages.

FEATURES

—Active Current Less Than 1 mA

—Typical Write Cycle Time of 5 ms

—Bidirectional Data Transfer Protocol

—Minimizes Total Write Time Per Byte

—Endurance: 100,000 Cycles

—Data Retention: 100 Years

© Xicor, 1991 Patents Pending

Characteristics subject to change without notice

1K

X24012

128 x 8 Bit

Serial E

FUNCTIONAL DIAGRAM

3847 FHD F01

3847-1

IC MICROSYSTEMS

TM