SY75608 datasheet(28/44 Pages) MICROCHIP

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SY75608/612

DS20006363D-page 28

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2021 - 2023 Microchip Technology Inc. and its subsidiaries

XTAL Load Capacitance - XTALLC (0x02)

7:0

xtal_load_cap[7:0]

Internal load capacitance of crystal circuit (0 pF to

23.8 pF with the resolution of 0.1875 pF).

XIN and XOUT have each capacitor connected to

GND.

Multiple bit combinations available between 7

capacitors.

8’b0000_0000 = Disable all xtal load capacitors

8’b0000_0001 = Enable capacitor 0.1875 pF

8’b0000_0010 = Enable capacitor 0.375 pF

8’b0000_0100 = Enable capacitor 0.75 pF

8’b0000_1000 = Enable capacitor 1.5 pF

8’b0001_0000 = Enable capacitor 3 pF

8’b0010_0000 = Enable capacitor 6 pF

8’b0100_0000 = Enable capacitor 12 pF

8’b1000_0000 = Reserved

R/W

Note 1

XTAL Normal Run - XTALNR (0x03)

7:1

Unused

0000000

xtal_normal_run

When this bit is set high crystal oscillator circuit is

running only if input_select[1:0] register at address

0x05 selects crystal mode (2’b10). This value is

recommended because it provides best jitter

performance—XO circuit is running only when it is

needed.

When this bit is set low the crystal oscillator will keep

running even if crystal oscillator is not selected in

input_select[1:0] register at address 0x05. This mode

should only be used when fast switching between

input references and crystal oscillator is required.

R/W

Note 1

Input Select - INSEL (0x04)

7:2

Unused

000000

1:0

input_select[1:0]

Input reference clock selection.

Proper external coupling and termination are

required.

2’b00 = Differential input from IN0_p and IN0_n

2’b01 = Differential input from IN1_p and IN1_n

2’b10 = Fundamental XTAL mode with XIN and XOUT

(Use internal crystal oscillator circuits) or XTAL

overdrive mode (single-ended clock signal fed to XIN)

2’b11 = XTAL bypass mode (single-ended clock signal

with XIN and disabled internal crystal buffer circuit in

the analog block)

R/W

Note 1

State of Outputs when Disabled (Outputs 0 to 3) - OUTDSTATE0 (0x05)

7:6

out_disable_state[7:6]

State of OUT3 driver when the corresponding bit in

OUTEN register is set low.

The same bit configuration with OUT0.

R/W

5:4

out_disable_state[5:4]

State of OUT2 driver when the corresponding bit in

OUTEN register is set low.

The same bit configuration with OUT0.

R/W

TABLE 6-2:

DETAILED REGISTER MAP (CONTINUED)

Bit

Name

Description

Type

Reset

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