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TUSB2036

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SLLS372I – MARCH 2000 – REVISED MARCH 2017

Product Folder Links: TUSB2036

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Copyright © 2000–2017, Texas Instruments Incorporated

Pin Functions (continued)

PIN

I/O

DESCRIPTION

NAME

NO.

(1)

If the hub is implemented to be bus-powered (via BUSPWR tying to GND):

(a) TUSB2036 reports to the host that the hub end-product downstream ports are power-switched (this is required by the USB 2.0

specification). Hub end-product vendor has to ensure the actual end-product implementation meets this specification requirement.

(b) Pin 21 acts as overcurrent protection (OCPROT) implementation indication pin for the bus-powered hub. The overcurrent protection

implementation is reported through the wHubCharacteristics. D4 bit in the hub descriptor.

(c) When OCPROT is low, the TUSB2036 reports to the host that the hub end-product provides overcurrent protection and the

wHubCharacteristics. D4 bit is set to 0.

(d) When OCPROT is high, the TUSB2036 reports to the host that the hub end-product does not provide overcurrent protection and the

wHubCharacteristics. D4 bit is set to 1.

(2)

If the hub is implemented to be self-powered (via BUSPWR tying to 3.3-V VCC):

(a) TUSB2036 reports to the host that the hub end-product provides overcurrent protection to the downstream ports (this is required by

the USB 2.0 specification). Hub end-product vendor has to ensure the actual end-product implementation meets this specification

requirement.

(b) Pin 21 acts as power switching (PWRSW) implementation indication pin for the self-powered hub. The power-switching

implementation is reported through the bPwrOn2PwrGood field in the hub descriptor.

(c) When PWRSW is low, the TUSB2036 reports to the host that the hub end-product has port power switching at the downstream ports

and the bPwrOn2PwrGood is set to 50 units (100 ms).

(d) When PWRSW is high, the TUSB2036 reports to the host that the hub end-product does not have port power switching at the

downstream ports and the bPwrOn2PwrGood is set to 0 units (0 ms).

OCPROT/

PWRSW

21

I

Overcurrent Protection for bus-powered hub (active low). /Power Switching for self-powered hub (active low). The

pin has a different meaning for the bus or self-powered hub. If the pin is logic high the internal pulldown is

disabled.(1) (2)

OVRCUR1

10

I

Overcurrent input. OVRCUR1

− OVRCUR3 are active low. For per-port overcurrent detection, one overcurrent

input is available for each of the three downstream ports. In the ganged mode, any OVRCUR input may be used

and all OVRCUR pins must be tied together. OVRCUR pins are active low inputs with noise filtering logic. Each

OVRCURn input is sampled every 2 ms and any input which is valid for two consecutive samples will be passed to

the internal logic. OVRCUR3 has an internal pull-up that can be enabled for the 2-port operation.

OVRCUR2

14

OVRCUR3

18

PWRON1

9

O

Power-on/-off control signals. PWRON1–PWRON3 are active low, push-pull outputs that enables the external

power switch device. Push-pull outputs eliminate the pullup resistors which open-drain outputs require. However,

the external power switches that connect to these pins must be able to operate with 3.3-V inputs because these

outputs cannot drive 5-V signals.

PWRON2

13

PWRON3

17

RESET

4

I

RESET is an active low TTL input with hysteresis and must be asserted at power up. When RESET is asserted,

all logic is initialized. Generally, a reset with a pulse width between 100 μs and 1 ms is recommended after 3.3-V

VCC reaches its 90%. Clock signal has to be active during the last 60 μs of the reset window.

SUSPND

32

O

Suspend status. SUSPND is an active high output available for external logic power-down operations. During the

suspend mode, SUSPND is high. SUSPND is low for normal operation.

MODE

31

I

Mode select. When MODE is low, the APLL output clock is selected as the clock source to drive the internal core

of the device and 6-MHz crystal or oscillator can be used. When MODE is high, the clock on XTAL1/CLK48 is

selected as the clock source and 48-MHz oscillator or other on-board clock source can be used.

NP3

24

I

Number of ports is 3. Active low input. A logic 0 configures the system to use 3 ports. A logic 1 configures the

system to use 2 ports.

NPINT0

22

I

Number of ports internal to hub system, which are permanently attached (see Table 1).

NPINT1

23

VCC

3, 25

I

3.3-V supply voltage

XTAL1/CLK48

30

I

Crystal 1/48-MHz clock input. When MODE is low, XTAL1/CLK48 is a 6-MHz crystal input with 50% duty cycle. An

internal APLL generates the 48-MHz and 12-MHz clocks used internally by the ASIC logic. When MODE is high,

XTAL1/CLK48 acts as the input of the 48-MHz clock and the internal APLL logic is bypassed.

XTAL2

29

O

Crystal 2. XTAL2 is a 6-MHz crystal output. This pin must be left open when using an oscillator.