LM2502

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SNLS176L – JANUARY 2004 – REVISED MAY 2013

PHASE-LOCKED LOOP

When the LM2502 is configured as a Master, a PLL is enabled to generate the serial link clock. The Phase-

locked loop system generates the serial data clock at several multiples of the input clock. The PLL operates with

an input clock between 3 and 26 MHz. See Table 12 below, Multiplier/Divisor times CLK rate must also be less

than 76.8 MHz. The 76.8 MHz limitation is based on the semiconductor process used on this implementation—it

is not an MPL limitation.

Line rate should also be selected such that it is faster than the input load rate when bursting data across the link.

Otherwise 8/10 X Line rate must be greater than the input load rate to the Master. At the maximum raw data rate

of 307 Mbps, the maximum information rate is 245 Mbps. Thus the parallel load rate at the Master input must not

exceed 15.4 Mega Transfers per second sustained (of 16 data bits). The Master can accommodate up to four

words at a higher rate due to internal FIFOs.

Configuration pins (PLL_CON[2:0], and M/S*) are used to determine the mode of which the part is operating in.

In the Slave configuration the PLL block is disabled. The Slave PLL_CON pins are required to set up the proper

divisor for the CLK pin. Slave PLL_CON[2:0] pins do not need to be set the same as the Master, this allows for

clock multiplication / division to be supported for the output clock reference signal.

RESET

On both the Master and the Slave, the PD* pin resets the logic. The PD* pins should be held low until the power

supply has ramped up and is stable and within specifications. The Slave PD* pin should be driven High first or at

the same time as the Master. This will ensure that the Slave sees the start up sequence from the Master.

MASTER/SLAVE SELECTION

The M/S* pin is used to configure the device as either a Master or Slave device. When the M/S* pin is a Logic

High, the Master configuration is selected. The Driver block is enabled for the MC line, and the MD lines. When

the M/S* pin is a Logic Low, the Slave configuration is selected. The Receiver block is enabled for the MC line,

and the MD lines.

Table 12. PLL_CON Settings

Multiplier

Divisor

Maximum

Minimum

PLLCON2

PLLCON1

PLLCON0

(Master)

(Slave)

CLK Input

CLK Input

MC out

CLKout

(MC

≦

≦ 76.8 MHz)

0

0

0

CLK X 2

MC / 2

13 MHz

26 MHz

0

0

1

CLK X 4

MC / 4

6 MHz

19.2 MHz

0

1

0

CLK X 6

MC / 6

3 MHz

12.8 MHz

0

1

1

CLK X 7

MC / 7

3 MHz

10.97 MHz

1

0

0

CLK X 8

MC / 8

3 MHz

9.60 MHz

1

0

1

CLK X 9

MC / 9

3 MHz

8.53 MHz

1

1

0

CLK X 10

MC / 10

3 MHz

7.68 MHz

1

1

1

(Reserved)

APPLICATION INFORMATION

SYSTEM CONSIDERATIONS

When employing the MPL SERDES chipset in place of a parallel bus, a few system considerations must be

taken into account. Before sending commands (ie initialization commands) to the display, the SERDES must be

ready to transmit data across the link. The MPL link must be powered up, and the PLL must be locked. Also a

review of the Slave output timing should be completed to insure that the timing parameters provided by the Slave

output meet the requirements of the LCD driver input. Specifically, pulse width on CSn*, RD* / WR*, data valid

time, and bus cycle rate should be reviewed and checked for inter-operability. Additional details are provided

next:

The MPL link should be started up as follows: The chipset should be powered up first, VDDIO should not be

powered up first, it may be at the same time as VDD/VDDA or lag. During power up, the PD* inputs should be held

LOW and released once power is stable and within specification. The Slave PD* may be released first or at the

same time as the Master. CLK should be applied prior to releasing PD*.

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