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6 - 16

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CMOS Control Voltages

Truth Table

Serial Data Input

Attenuation

Setting

RF1 - RF2

C1

C2

C4

C8

C16

High

High

High

High

High

Reference

I.L.

Low

High

High

High

High

1 dB

High

Low

High

High

High

2 dB

High

High

Low

High

High

4 dB

High

High

High

Low

High

8 dB

High

High

High

High

Low

16 dB

Low

Low

Low

Low

Low

31 dB

Max. Atten.

Any combination of the above states will provide an attenuation

approximately equal to the sum of the bits selected.

State

Vcc = +5V

Vcc = +3V

Low

0 to 1.3V

0 to 0.7V

High

3.5 to 5.0V

2.3 to 3.0V

-1.2

-1

-0.8

-0.6

-0.4

-0.2

0

0.2

0.4

0.6

0.8

1

1.2

0.5

1

1.5

2

2.5

3

3.5

4

FREQUENCY (GHz)

Worst Case Step Error

Between Successive Attenuation States

Timing Diagram

1 dB LSB GaAs MMIC 5-BIT SERIAL

CONTROL DIGITAL ATTENUATOR, 0.7 - 3.7 GHz

v02.0705

Serial Input Truth Table

Latch

Enable

Shift

Clock

Reset

Function

X

X

L

Shift register cleared

X

H

Shift register clocked

XH

Contents of shift register

transferred to Digital

Attenuator

Parameter

Symbol

Vcc = +5V

Vcc = +3V

Units

Min.

Max.

Min.

Max.

Serial Input Setup

Time

ts

20

-

100

-

ns

Hold time from Serial

Input to Shift Clock

th

0

-

5

-

ns

Setup time from

Shift Clock to Latch

Enable

tlsup

40

-

100

-

ns

Propagation delay,

Latch Enable to C1

through C16

tpd

-

30

-

70

ns

Setup time from

Reset to Shift Clock

-20

-

50

-

ns

Clock Frequency

(1/tclk)

fclk

-

30

-

10

MHz

Timing