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74ACT109PC データシート(PDF) 7 Page - ON Semiconductor

部品番号 74ACT109PC
部品情報  Dual JK Positive Edge-Triggered Flip-Flop
PDF  12 Pages
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74ACT109PC データシート(HTML) 7 Page - ON Semiconductor

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©1988 Fairchild Semiconductor Corporation
www.fairchildsemi.com
74AC109, 74ACT109 Rev. 1.5
7
AC Electrical Characteristics for ACT
Note:
8. Voltage range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
Note:
9. Voltage range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
VCC (V)
(8)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Units
Min.
Typ. Max.
Min.
Max.
fMAX
Maximum Clock Frequency
5.0
145
210
125
MHz
tPLH
Propagation Delay,
CPn to Qn or Qn
5.0
4.0
7.0
11.0
3.5
13.0
ns
tPHL
Propagation Delay,
CPn to Qn or Qn
5.0
3.0
6.0
10.0
2.5
11.5
ns
tPLH
Propagation Delay,
CDn or SDn to Qn or Qn
5.0
2.5
5.5
9.5
2.0
10.5
ns
tPHL
Propagation Delay
5.0
2.5
6.0
10.0
2.0
11.5
ns
CDn or SDn to Qn or Qn
Symbol
Parameter
VCC (V)
(9)
TA = +25°C,
CL = 50pF
TA = –40°C to +85°C,
CL = 50pF
Units
Typ.
Guaranteed Minimum
tS
Setup Time, HIGH or LOW,
Jn or Kn to CPn
5.0
0.5
2.0
2.5
ns
tH
Hold Time, HIGH or LOW,
Jn or Kn to CPn
5.0
0
2.0
2.0
ns
tW
Pulse Width,
CPn or CDn or SDn
5.0
3.0
5.0
6.0
ns
trec
Recovery Time,
CDn or SDn to CPn
5.0
–2.5
0
0
ns
Symbol
Parameter
Conditions
Typ.
Units
CIN
Input Capacitance
VCC = OPEN
4.5
pF
CPD
Power Dissipation Capacitance
VCC = 5.0V
35.0
pF



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