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ADS5295IPFP データシート(PDF) 8 Page - Texas Instruments

部品番号 ADS5295IPFP
部品情報  12-Bit, 100-MSPS, 8-Channel Analog-to-Digital Converter
PDF  93 Pages
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メーカー  TI2 [Texas Instruments]
ホームページ  https://www.ti.com
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ADS5295IPFP データシート(HTML) 8 Page - Texas Instruments

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ADS5295
SBAS595 – DECEMBER 2012
www.ti.com
Table 1. Two-Wire, 12x Serialization(1)(2)
tPDI = (11/12) × tS + tDELAY
Where tDELAY is specified as
SETUP TIME (ns)
HOLD TIME (ns)
below, ns
SAMPLING
FREQUENCY (MSPS)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
10
7.80
8.00
8.5
11
13.5
30
2.40
2.50
8.5
11
13.5
50
1.10
1.60
8.5
11
13.5
65
0.83
1.25
8.5
11
13.5
80
0.60
1.00
8.5
11
13.5
100
0.52
0.62
8.5
11
13.5
(1)
All the timing specifications are taken with default output clock and data delay settings (0 ps).
(2)
Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for output clock and data delay
options.
Table 2. One-Wire, 12x Serialization(1)(2)
tPDI = (9/12) × tS + tDELAY
Where tDELAY is specified as
SETUP TIME (ns)
HOLD TIME (ns)
below, ns
SAMPLING
FREQUENCY (MSPS)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
10
3.90
4.00
8
10
12
30
1.00
1.30
8
10
12
50
0.60
0.57
8
10
12
65
0.40
0.34
8
10
12
80
0.22
0.24
8
10
12
(1)
All the timing specifications are taken with default output clock and data delay settings (0 ps).
(2)
Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for output clock and data delay
options.
Table 3. Two-Wire, 10x Serialization(1)(2)
SETUP TIME (ns)
HOLD TIME (ns)
SAMPLING FREQUENCY
(MSPS)
MIN
TYP
MAX
MIN
TYP
MAX
65
1.00
1.50
80
0.74
1.20
100
0.44
1.00
(1)
All the timing specifications are taken with default output clock and data delay settings (0 ps).
(2)
Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for output clock and data delay
options.
Table 4. One-Wire, 10x Serialization(1)(2)
SETUP TIME (ns)
HOLD TIME (ns)
SAMPLING FREQUENCY
(MSPS)
MIN
TYP
MAX
MIN
TYP
MAX
65
0.51
0.60
80
0.33
0.36
100
0.17
0.31
(1)
All the timing specifications are taken with default output clock and data delay settings (0 ps).
(2)
Refer to the Programmable LVDS Output Clock and Data Edges section in the Application Information for output clock and data delay
options.
8
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Product Folder Links: ADS5295



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