L9679E datasheet(77/127 Pages) STMICROELECTRONICS

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For all conditions the current on SFx/SRx pins will not exceed the VRCM current limitation value (ILIM_VRCM_SINK

or ILIM_VRCM_SRC). There may be higher currents on the squib/pyroswitch lines due to the presence of filter

capacitors. During these FET tests, energy available to the squib/pyroswitch is limited to less than EFET_TEST. For

high side FET diagnostics, if no faults were indicated in the preceding leakage diagnostics then a normal result

would be [STB=1, STG=0]. If the returned result for the high side FET test is not as the previous then either the

FET is not functional, a short to ground occurred during the test, or there is a missing SSxy connection for that

channel.

For low-side FET diagnostics if no faults were indicated in the preceding leakage diagnostics then a normal result

would be [STB=0, STG=1]. If the returned result for the low-side FET test is not as the previous then either the

FET is not functional or a short to battery occurred during the test. In case of ground loss the low-side FET

diagnostic would not indicate a FET fault.

The VRCM flags will be given in the LPDIAGSTAT register. The status of the VRCM flags after FET test is latched

and can be cleared upon either LPDIAGREQ or SYSDIAGREQ SPI commands.

Finally, after FET test is completed, the VRCM deglitch filter time is switched from the FET test deglitch filter time

(TFLT_LKGB_FT) to the leakage diagnostic test deglitch filter time (TFLT_LKG) for both HS and LS and the output of

the VRCM deglitch filter is now not allowed to disable the appropriate HS or LS squib/pyroswitch driver anymore.

Loss of ground return diagnostics

This diagnostics is available during a squib/pyroswitch measurement. This test is based on the voltage drop

across the ground return, if the voltage drop exceeds SGxy_OPEN, ground connection is considered as lost.

Should the ground connection on the squib/pyroswitch driver circuit be missing, the bit related to the channel

under test by the two above diagnostics will be activated in the LP_GNDLOSS register. The flag is latched after a

proper filter time TFLT_SGOPEN and cleared upon read.

High-side safing FET diagnostics

The user can measure the voltage levels of the SSxy nodes. If the safing FET is properly switched on, the voltage

on SSxy will be regulated.

The measurement request is done via Diagnostic Control command (DIAGCTRLx), while results will be reported

through ADCRESx bit fields.

Deployment timer diagnostic

This test allows to verify the correct functionality and duration of the timers used to control the deployment times.

This test can be executed only when the IC is in the Diag state by setting the appropriate code in the DSTEST

field of the SYSDIAGREQ register. When the test is launched, the IC sequentially triggers the activation of the

deployment timers of the various channels (each of them separated by 8ms idle time) and outputs the relevant

waveform to the FENL output discrete pin, which will act as an output pin only for this test (put an external resistor

to limit the current if double driver condition is present).

Additional test is available to check operation of FENL output buffer through dedicated value of DSTEST field.

To understand the sequence of deployment timer test look at Figure 17. Deployment timer diagnostic sequence.

The µC can therefore test the deployment times by measuring the duration of the high pulses sent by the IC on

the FENL pin. The deployment time configuration used during this test is the latest one programmed in the DCRx

registers. In case the test is run on a channel with no DCRx deployment time previously configured, a default 8 µs

high pulse is output on FENL for the relevant channel.

L9679E

Deployment drivers

DS12485 - Rev 8

page 77/127

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