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L9679P データシート(PDF) 33 Page - STMicroelectronics |
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L9679P データシート(HTML) 33 Page - STMicroelectronics |
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33 / 279 page ![]() DS11627 Rev 7 33/279 L9679P Start-up and power control 278 6.2.5 Power-up and power-down sequences The behaviour of the IC during normal power-up and power-down is shown from Figure 6 to Figure 9. The following sequences represent just a subset of all possible power-up and power-down scenarios. In Figure 6 a normal IC power-up controlled by the state of the WAKEUP pin is shown. Figure 6. Normal power-up sequence VBBAD VBGOOD VBAT _MON WAKE UP 4ms <1ms WU_on VINT POR ERBSTSW and SYNCBSTSW ERBOOST VER VCC RESET <50 A VIN current WU_mon >1ms VIN-Vdiode 0V SYNCBOOST_OK VIN-Vdiode SYNCBOOST SAT BCKSW SATBUCK_OK SATBUCK VCCBCKSW VCC_UV <50 A WU_off VINT_UV 0V 0V 0V 0V 0V SPI_SYS_CTL(ER_CUR_EN)=01 VIN VINBAD VINGOOD SPI command RESET output buffer disabled – only passive pull down keep low the RESET pin RESET output buffer active Reset_hold_time VCCSEL VTH1_H_VCCSEL VCORE 0V 0V GADG1406180758PS |
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