CB35000 datasheet(10/16 Pages) STMICROELECTRONICS

10 / 16 page

CB35000 SERIES

10/16

DESIGN ENVIRONMENT

Several interface levels are possible between

SGS-THOMSON

and

the

customer

the

undertaking of an ASIC design. The four levels of

interface are shown in Figure 7. Level 1 is

characterized by SGS-THOMSON receiving the

system speciﬁcation and taking the design

through to validation and fabrication. At level 2

interface the designer supplies a complete logic

design implemented in a standard generic logic

family. SGS-THOMSON then takes the design

through to layout, validation and fabrication.

Level 3 is the most common and preferred

interface level. Logic capture and pre-layout

Figure 7

Customer/SGS-THOMSON Interface Levels

SYSTEM

SPECIFICATION

LOGIC

DESIGN

SCHEMATIC

CAPTURE

DESIGN

VERIFICATION

PRE-LAYOUT

SIMULATION

LAYOUT

POST-LAYOUT

SIMULATION

LEVEL 1

LEVEL 2

LEVEL 3

LEVEL 4

CUSTOMER

SGS-THOMSON

MANUFACTURE

AND TEST

ECR1

ECR2

simulation are performed by the designer using

an SGS-THOMSON supported design kit. The

design is then taken through layout, validation

and fabrication by SGS-THOMSON.

The SGS-THOMSON design system validates all

designs before fabrication. Design kits are

provided that allow schematic capture entry via

Mentor

Graphics

and

Cadence

products.

Simulation is supported for Cadence and Mentor

Graphics. Full support is also provided for

Cadence Verilog, Synopsys VSS and System

Hilo simulators. Figure 8 shows the SGS-

THOMSON Design Flow.

Test vector development uses TSSI software

from Summit and Currentest from CrossCheck.

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