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L9300 データシート(PDF) 41 Page - STMicroelectronics |
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L9300 データシート(HTML) 41 Page - STMicroelectronics |
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41 / 178 page  9 Reset 9.1 Resets outputs 9.1.1 Reset outputs functional description The device provides two different reset signals RES1 and RES2: RES1 is the logic OR of VDD3 undervoltage/ overvoltage, VDD4 undervoltage/overvoltage and watchdog fault (details on watch dog reset conditioning is reported in the watchdog section). RES2 is triggered only by an undervoltage or overvoltage on VDD3. Both RES1 and RES2 are open drain circuits. RES1 is bidirectional. When the RES1 is driven low (by internal or external command) automatically all the drivers are disabled. An echo of reset signal driven low from external condition is detected and latched into Service Fault SPI register to let the microcontroller understand the fault generation mechanism after the reset signal disappears. Both the reset signals are active low. Figure 22. Reset generation GADG1707170843PS L9300 Reset DS12258 - Rev 5 page 41/178 |
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