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L9942 データシート(PDF) 22 Page - STMicroelectronics |
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L9942 データシート(HTML) 22 Page - STMicroelectronics |
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22 / 40 page ![]() Functional description of the logic with SPI L9942 22/40 Doc ID 11778 Rev 7 Note: Due to this safety functionality a daisy chaining of SPI is not possible. Instead, a parallel operation of the SPI bus by controlling the CSN signal of the connected ICs is recommended. 4.6 Serial data out (DO) The data output driver is activated by a logical low level at the CSN input and will go from high impedance to a low or high level depending on the status bit 0 (fault condition). The first rising edge of the CLK input after a high to low transition of the CSN pin will transfer the content of the selected status register into the data out shift register. Each subsequent falling edge of the CLK will shift the next bit out. 4.7 Serial clock (CLK) The CLK input is used to synchronize the input and output serial bit streams. The data input (DI) is sampled at the rising edge of the CLK and the data output (DO) will change with the falling edge of the CLK signal. 4.8 Data register The device has eight data registers. The first three bits (bit 0 ... bit 2) at the DI-input are used to select one of the input registers. All bits are first shifted into an input shift register. After the rising edge of CSN the contents of the input shift register will be written to the selected Input Data Register only if a frame of exact 16 data bits are detected. The selected register will be transferred to DO during the current communication frame. Figure 9. SPI and registers D DI CLK_ADR D1 A1 D0 A2 D3 D4 D5 D6 D7 D8 D9 D10 D11 DO DIR Register 0 AI0 AI1 AI2 AI3 AI4 BI0 BI1 BI2 BI3 BI4 DAC Phase B DAC Phase A Register 2 P0 P1 P2 P3 P4 Phase A Phase B Register 7 D2 D12 Phase Counter Register 1 I0 I1 I2 I3 I4 I0 I1 I2 I3 I4 Current Profile 0 Current Profile 1 OVW OV Openload LSA1 HSA1 LSA2 HSA2 LSB1 LSB2 HSB1 HSB2 Overcurrent UV OV(W) CSN CLK INT_2MHz SPI- Controll POR Slew Rate Step Mode SR0 SR1 ST1 ST0 DAC_Scale DC1 DC2 Temperature VS Monitor SEL_ERROR SPI2REG D A1 A0 A2 TSD TW RREF Error CLR7 CLR6 Read-Only DC0 Read Only PWM Freq FT I0 I1 I2 I3 I4 Current Profile 8 Read-Only ST I0 I1 I2 I3 I4 I0 I1 I2 I3 I4 Current Profile 2 Current Profile 3 NPWM D0 D1 PWM Counter I0 I1 I2 I3 I4 I0 I1 I2 I3 I4 Current Profile 4 Current Profile 5 I0 I1 I2 I3 I4 I0 I1 I2 I3 I4 Current Profile 6 Current Profile 7 Decay Mode DM0 DM1 DM2 SST A0 Test only PWM PWM Counter PWM Counter D5 D6 D7 D2 D3 D4 T0 T1 Register 3 Register 4 Register 5 Register 6 |
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